System and method for connecting peripheral buses through a serial bus

• US 6,425,033 B1
• Filed: 06/05/1998
• Issued: 07/23/2002
• Est. Priority Date: 06/20/1997
• Status: Expired due to Term

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Schultz, Kevin, Conway, Craig M., Sescila, Glen, Hormuth, Robert, Odom, B. Keith, Sabolcik, Ross, Mitchell, Bob
• Primary Examiner(s): Beausoleil, Robert
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US09/092,342
• Time in Patent Office: 1,509 Days
• Field of Search: 710/101-103, 710/128-129, 710/2, 710/4, 710/31, 710/36, 710/28, 710/62, 710/63, 710/64, 710/71, 710/72-74, 710/127, 710/126
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge. Each of the primary bridge and secondary bridge include parallel/serial transceivers for converting parallel data generated on the first PCI bus and second PCI bus, respectively, to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first PCI bus and second PCI bus, respectively. The primary bridge and the secondary bridge collectively implement a PCI—PCI bridge register set.

Claims

1. A system for connecting peripheral devices to a computer, comprising:

a computer system, wherein the computer system includes a CPU and memory, wherein the computer system includes;

a first Peripheral Component Interconnect (PCI) bus; and

a primary interface coupled to the first PCI bus, wherein the primary interface includes PCI interface circuitry for interfacing to the first PCI bus;

a remote device located remotely from the computer system, the remote device comprising;

a second PCI bus;

one or more peripheral devices coupled to the second PCI bus; and

a secondary interface coupled to the second PCI bus, wherein the secondary interface includes PCI interface circuitry for interfacing to the second PCI bus;

a serial bus coupled between the primary interface and the secondary interface, wherein the serial bus includes first and second ends, wherein the first end of the serial bus is coupled to the primary interface and the second end of the serial bus is coupled to the secondary interface;

wherein the primary interface and the secondary interface operate as a single PCI—

PCI bridge;

wherein the primary interface and the secondary interface collectively implement a PCI—

PCI bridge register set; and

wherein the primary interface operates as a first portion of a PCI—

PCI bridge, and wherein the secondary interface operates as a second portion of the PCI—

PCI bridge.

2. The system of claim 1, wherein the primary interface and the secondary interface are operable to transmit PCI bus cycles over the serial bus.

3. The system of claim 1, wherein the primary interface is operable to receive first PCI cycles on the first PCI bus and generate first serial data on the serial bus in response thereto;

wherein the secondary interface is operable to receive the first serial data from the serial bus and generate second PCI cycles on the second PCI bus.

4. The system of claim 3, wherein the secondary interface is operable to receive third PCI cycles on the second PCI bus and generate second serial data on the serial bus in response thereto;

wherein the primary interface is operable to receive the second serial data from the serial bus and generate fourth PCI cycles on the first PCI bus.

5. The system of claim 1, wherein the CPU in the computer system is operable to generate cycles on the first PCI bus to communicate with the one or more peripheral devices coupled to the second PCI bus.

6. The system of claim 1, wherein each of the primary interface and the secondary interface include parallel/serial transceivers for converting parallel data generated on the first PCI bus and second PCI bus, respectively, to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first PCI bus and second PCI bus, respectively.

7. The system of claim 1, wherein the CPU is operable to generate cycles on the first PCI bus to communicate with a peripheral device, wherein the peripheral device is coupled to either the first PCI bus or the second PCI bus.

8. The system of claim 1, wherein the memory of the computer system stores software, wherein the software is executable to communicate with a peripheral device coupled to either the first PCI bus or the second PCI bus.

9. The system of claim 1, wherein the memory of the computer system stores software, wherein the software was developed to communicate with a first peripheral device coupled to the first PCI bus of the host computer;

wherein the software is executable to communicate with the first peripheral device coupled to either the first PCI bus or the second PCI bus.

10. The system of claim 1, wherein, to the CPU, the one or more peripheral devices coupled to the second PCI bus appear coupled to the first PCI bus.

11. The system of claim 1, wherein the one or more peripheral devices coupled to the second PCI bus are virtually coupled to the first PCI bus.

12. The system of claim 1, wherein the serial bus has a length greater than one meter.

13. The system of claim 1, wherein the serial bus has a length that ranges from 2 meters to 2 kilometers.

14. The system of claim 1, wherein the computer system has a first mechanical form factor, wherein the remote device has a second mechanical form factor, wherein the second mechanical form factor is different than the first mechanical form factor.

15. The system of claim 14, wherein the second mechanical form factor is a more rugged mechanical form factor than the first mechanical factor.

16. The system of claim 1, wherein the serial bus is a high-speed IEEE 1394 or IEEE 1394.2 serial bus.

17. The system of claim 1, wherein the primary interface, the secondary interface, and the serial bus collectively implement a PCI—

PCI bridge.

18. The system of claim 1, wherein the primary interface operates as a first half of a PCI—

PCI bridge, and wherein the secondary interface operates as a second half of the PCI—

PCI bridge.

19. A system for connecting peripheral devices to a computer, comprising:

a computer system, wherein the computer system includes a CPU and memory;

a first Peripheral Component Interconnect (PCI) bus coupled to the computer system;

a primary interface coupled to the first PCI bus, wherein the primary interface includes PCI interface circuitry for interfacing to the first PCI bus;

a second PCI bus located remotely from the computer system;

one or more devices coupled to the second PCI bus; and

a secondary interface coupled to the second PCI bus, wherein the secondary interface is located remotely from the computer system, wherein the secondary interface includes PCI interface circuitry for interfacing to the second PCI bus; and

a serial bus coupled between the primary interface and the secondary interface, wherein the serial bus includes first and second ends, wherein the first end of the serial bus is coupled to the primary interface and the second end of the serial bus is coupled to the secondary interface;

wherein the primary interface and the secondary interface operate as a single PCI—

PCI bridge;

wherein the primary interface and the secondary interface collectively implement a PCI—

PCI bridge register set; and

wherein the primary interface operates as a first portion of a PCI—

PCI bridge, and

wherein the secondary interface operates as a second portion of the PCI—

PCI bridge.

20. The system of claim 19, wherein the primary interface and the secondary interface are operable to transmit PCI bus cycles over the serial bus.

21. The system of claim 19, wherein the primary interface is operable to receive first PCI cycles on the first PCI bus and generate first serial data on the serial bus in response thereto;

wherein the secondary interface is operable to receive the first serial data from the serial bus and generate second PCI cycles on the second PCI bus.

22. The system of claim 21, wherein the secondary interface is operable to receive third PCI cycles on the second PCI bus and generate second serial data on the serial bus in response thereto;

wherein the primary interface is operable to receive the second serial data from the serial bus and generate fourth PCI cycles on the first PCI bus.

23. The system of claim 19, wherein the CPU in the computer system is operable to generate cycles on the first PCI bus to communicate with the one or more devices coupled to the second PCI bus.

24. The system of claim 19, wherein each of the primary interface and the secondary interface include parallel/serial transceivers for converting parallel data generated on the first PCI bus and second PCI bus, respectively, to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first PCI bus and second PCI bus, respectively.

25. The system of claim 19, wherein the CPU is operable to generate cycles on the first PCI bus to communicate with a device, wherein the device is coupled to either the first PCI bus or the second PCI bus.

26. The system of claim 19, wherein the memory of the computer system stores software, wherein the software is executable to communicate with a device coupled to either the first PCI bus or the second PCI bus.

27. The system of claim 19, wherein the memory of the computer system stores software, wherein the software was developed to communicate with a first device coupled to the first PCI bus of the host computer;

wherein the software is executable to communicate with the first device coupled to either the first PCI bus or the second PCI bus.

28. The system of claim 19, wherein, to the CPU, the one or more devices coupled to the second PCI bus appear coupled to the first PCI bus.

29. The system of claim 19, wherein the one or more devices coupled to the second PCI bus are virtually coupled to the first PCI bus.

30. The system of claim 19, wherein the serial bus has a length greater than one meter.

31. The system of claim 19, wherein the serial bus has a length that ranges from 2 meters to 2 kilometers.

32. The system of claim 19, wherein the computer system has a first mechanical form factor;

wherein the secondary interface, the second PCI bus, and the one or more devices are comprised in a remote system, wherein the remote system has a second mechanical form factor, wherein the second mechanical form factor is different than the first mechanical form factor.

33. The system of claim 32, wherein the second mechanical form factor is a more rugged mechanical form factor than the first mechanical factor.

34. The system of claim 19, wherein the serial bus is a high-speed IEEE 1394 or IEEE 1394.2 serial bus.

35. The system of claim 19, wherein the primary interface, the secondary interface, and the serial bus collectively implement a PCI—

PCI bridge.

36. The system of claim 19, wherein the primary interface operates as a first half of a PCI—

PCI bridge, and wherein the secondary interface operates as a second half of the PCI—

PCI bridge.

50. The system of claim 34, wherein the first bus is a Peripheral Component Interconnect (PCI) bus.

37. A system for connecting peripheral devices to a computer, comprising:

a computer system, wherein the computer system includes a CPU and memory, wherein the computer system includes;

a first bus; and

a primary interface coupled to the first bus, wherein the primary interface includes first bus interface circuitry for interfacing to the first bus;

a remote device located remotely from the computer system, the remote device comprising;

a second bus;

one or more devices coupled to the second bus; and

a secondary interface coupled to the second bus, wherein the secondary interface includes second bus interface circuitry for interfacing to the second bus;

a serial bus coupled between the primary interface and the secondary interface, wherein the serial bus includes first and second ends, wherein the first end of the serial bus is coupled to the primary interface and the second end of the serial bus is coupled to the secondary interface;

wherein the primary interface and the secondary interface operate as a single bridge;

wherein the primary interface and the secondary interface collectively implement a single bridge register set of the single bridge; and

wherein the primary interface operates as a first portion of the bridge, and wherein the secondary interface operates as a second portion of the bridge.

38. The system of claim 37, wherein the primary interface and the secondary interface are operable to transmit first and second bus cycles over the serial bus.

39. The system of claim 37, wherein the primary interface is operable to receive first cycles on the first bus and generate first serial data on the serial bus in response thereto;

wherein the secondary interface is operable to receive the first serial data from the serial bus and generate second cycles on the second bus.

40. The system of claim 39, wherein the secondary interface is operable to receive third cycles on the second bus and generate second serial data on the serial bus in response thereto;

wherein the primary interface is operable to receive the second serial data from the serial bus and generate fourth cycles on the first bus.

41. The system of claim 37, wherein the CPU in the computer system is operable to generate cycles on the first bus to communicate with the one or more devices coupled to the second bus.

42. The system of claim 37, wherein each of the primary interface and the secondary interface include parallel/serial transceivers for converting parallel data generated on the first bus and second bus, respectively, to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first bus and second bus, respectively.

43. The system of claim 37, wherein the memory of the computer system stores software, wherein the software was developed to communicate with a first device coupled to the first bus of the host computer;

wherein the software is executable to communicate with the first device coupled to either the first bus or the second bus.

44. The system of claim 37, wherein the serial bus has a length greater than one meter.

45. The system of claim 37, wherein the serial bus has a length that ranges front 2 meters to 2 kilometers.

46. The system of claim 37, wherein the computer system has a first mechanical form factor, wherein the remote device has a second mechanical form factor, wherein the second mechanical form factor is different than the first mechanical form factor.

47. The system of claim 46, wherein the second mechanical form factor is a more rugged mechanical form factor than the first mechanical factor.

48. The system of claim 37, wherein the serial bus is a high-speed IEEE 1394 or IEEE 1394.2 serial bus.

49. The system of claim 37, wherein the primary interface, the secondary interface, and the serial bus collectively implement the single bridge.

51. The system of claim 37, wherein the second bus is a Peripheral Component Interconnect (PCI) bus.

52. The system of claim 37, wherein the first bus is a Peripheral Component Interconnect (PCI) bus, and wherein the second bus is a PCI bus;

wherein the single bridge is a PCI—

PCI bridge.

53. The system of claim 52, wherein the primary interface, the secondary interface, and the serial bus collectively implement the PCI—

PCI bridge.

54. The system of claim 53, wherein the primary interface and the secondary interface collectively implement the PCI—

PCI bridge register set.

55. The system of claim 53, wherein the primary interface operates as a first portion of the PCI—

PCI bridge, and wherein the secondary interface operates as a second portion of the PCI—

PCI bridge.

56. A bridge for expanding access over a first bus to a second bus, the bridge comprising:

a primary interface operable to couple to a first PCI bus, wherein the primary interface includes PCI interface circuitry for interfacing to the first PCI bus, wherein the primary interface further includes a serial interface for interfacing to a serial bus;

a secondary interface operable to couple to a second PCI bus, wherein the secondary interface includes PCI interface circuitry for interfacing to the second PCI bus, wherein the secondary interface further includes a serial interface for interfacing to the serial bus, wherein the secondary interface is located, remotely from the primary interface; and

the serial bus coupled between the primary interface and the secondary interface, wherein the serial bus includes first and second ends, wherein the first end of the serial bus is coupled to the primary interface and the second end of the serial bus is coupled to the secondary interface;

wherein the primary interface and the secondary interface operate as a single PCI—

PCI bridge;

wherein the primary interface and the secondary interface collectively implement a PCI—

PCI bridge register set for the single PCI—

PCI bridge; and

wherein the primary interface operates as a first portion of the single PCI—

PCI bridge, and wherein the secondary interface operates as a second portion of the single PCI—

PCI bridge.

57. The bridge of claim 56, wherein the primary interface and the secondary interface are operable to transmit PCI bus cycles over the serial bus.

58. The bridge of claim 56, wherein the primary interface is operable to receive first PCI cycles on the first PCI bus and generate first serial data on the serial bus in response thereto;

wherein the secondary interface is operable to receive the first serial data from the serial bits and generate second PCI cycles on the second PCI bus.

59. The bridge of claim 58, wherein the secondary interface is operable to receive third PCI cycles on the second PCI bus and generate second serial data on the serial bus in response thereto;

wherein the primary interface is operable to receive the second serial data from the serial bus and generate fourth PCI cycles on the first PCI bus.

60. The bridge of claim 56, wherein each of the primary interface and the secondary interface include parallel/serial transceivers for converting parallel data generated on the first PCI bus and second PCI bus, respectively, to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first PCI bus and second PCI bus, respectively.

61. The bridge of claim 56, wherein the serial bus has a length greater than one meter;

wherein the secondary interface is located greater than one meter from the primary interface.

62. The system of claim 56, wherein the serial bus has a length that ranges from 2 meters to 2 kilometers;

wherein the secondary interface is located between 2 meters and 2 kilometers from the primary interface.

63. The system of claim 56, wherein the serial bus is a high-speed IEEE 1394 or IEEE 1394.2 serial bus.

64. The bridge of claim 56, wherein the primary interface, the secondary interface, and the serial bus collectively implement the single PCI—

PCI bridge.

65. A bridge for expanding access over a first bus to a second bus, the bridge comprising:

a primary interface operable to couple to a first bus, wherein the primary interface includes first bus interface circuitry for interfacing to the first bus, wherein the primary interface further includes a serial interface for interfacing to a serial bus;

a secondary interface operable to couple to a second bus, wherein the secondary interface includes second bus interface circuitry for interfacing to the second bus, wherein the secondary interface further includes a serial interface for interfacing to the serial bus, wherein the secondary interface is located remotely from the primary interface; and

the serial bus coupled between the primary interface and the secondary interface, wherein the serial bus includes first and second ends, wherein the first end of the serial bus is coupled to the primary interface and the second end of the serial bus is coupled to the secondary interface;

wherein the primary interface and the secondary interface operate as a single bridge;

wherein the primary interface and the secondary interface collectively implement a bridge register set for the single bridge; and

wherein the primary interface operates as a first portion of the single bridge, and wherein the secondary interface operates as a second portion of the single bridge.

66. The bridge of claim 65, wherein the primary interface and the secondary interface are operable to transmit bus cycles over the serial bus.

67. The bridge of claim 65, wherein the primary interface is operable to receive first bus cycles on the first bus and generate first serial data on the serial bus in response thereto;

wherein the secondary interface is operable to receive the first serial data from the serial bus and generate second bus cycles on the second bus.

68. The bridge of claim 67, wherein the secondary interface is operable to receive third bus cycles on the second bus and generate second serial data on the serial bus in response thereto;

wherein the primary interface is operable to receive the second serial data from the serial bus and generate fourth bus cycles on the first PCI bus.

69. The bridge of claim 65, wherein each of the primary interface and the secondary interface include parallel/serial transceivers for converting parallel data generated on the first bus and second bus, respectively, to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first bus and second bus, respectively.

70. The bridge of claim 65, wherein the serial bus has a length greater than one meter;

wherein the secondary interface is located greater than one meter from the primary interface.

71. The system of claim 65, wherein the serial bus has a length that ranges from 2 meters to 2 kilometers;

wherein the secondary interface is located between 2 meters and 2 kilometers from the primary interface.

72. The system of claim 65, wherein the serial bus is a high-speed IEEE 1394 or IEEE 1394.2 serial bus.

73. The bridge of claim 65, wherein the primary interface, the secondary interface, and the serial bus collectively implement the single bridge.

74. A first interface useable in expanding access over a first bus to a second bus, the first interface comprising:

first bus interface circuitry operable to couple to the first bus for interfacing to the first bus; and

a serial interface for interfacing to a serial bus;

wherein the first interface is operable to receive first bus cycles on the first bus and generate first serial data on the serial bus in response thereto;

wherein the first interface is operable to receive second serial data from the serial bus and generate second bus cycles on the first bus in response thereto;

wherein the first interface implements a first portion of a bridge;

wherein the first interface is operable to interface through the serial bus to a second interface, wherein the second interface is operable to interface to the second bus located at a remote location relative to the first bus;

wherein the first interface and the second interface operate as a single bridge; and

wherein the first interface implements at least a portion of a bridge register set for the single bridge.

75. The first interface of claim 74, further comprising:

parallel/serial transceivers for converting parallel data generated on the first bus to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first bus.

76. The bridge of claim 74, wherein the serial interface is operable to interface to a serial bus having a length greater than one meter;

wherein the second interface is operable to be located greater than one meter from the first interface.

77. The system of claim 74, wherein the first interface, the second interface, and the serial bus are operable to collectively implement a bridge register set for the single bridge.

78. The system of claim 74, wherein the first interface operates as a first portion of the single bridge, and wherein the second interface is operable to operate as a second portion of the single bridge.

79. The system of claim 74, wherein the first bus is the PCI bus;

wherein the first bus interface circuitry comprises PCI bus interface circuitry.