Multiprocessor operation in a multimedia signal processor

• US 6,425,054 B1
• Filed: 10/10/2000
• Issued: 07/23/2002
• Est. Priority Date: 08/19/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Nguyen, Le Trong
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Encarnacion, Yamir
• Application Number:
  US09/685,982
• Time in Patent Office: 651 Days
• Field of Search: 711/117, 711/118, 711/130, 711/140, 711/147, 711/149, 712/1-9, 712/24, 712/29, 712/32-35, 345/501-506, 345/514-522, 710/131, 710/132
• US Class Current: 711/117
• CPC Class Codes: G06F 15/8076 Details on data register access
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

To achieve high performance at low cost, an integrated digital signal processor uses an architecture which includes both a general purpose processor and a vector processor. The integrated digital signal processor also includes a cache subsystem, a first bus and a second bus. The cache subsystem provides caching and data routing for the processors and buses. Multiple simultaneous communication paths can be used in the cache subsystem for the processors and buses. Furthermore, simultaneous reads and writes are supported to a cache memory in the cache subsystem.

Claims

1. An integrated digital signal processor comprising:

a processing core that includes a first processor and a cache system having a cache control, wherein the first processor accesses an address space via the cache system;

a first plurality of different types of devices coupled to at least a first interface for accessing a first device that is external to the integrated digital signal processor;

a first bus that directly connects the cache system to the first plurality of different types of devices, wherein the first interface and the first bus operate at a first clock frequency;

a second plurality of different types of devices coupled to at least a second interface for accessing a second device that is external to the integrated digital signal processor; and

a second bus that directly connects the cache system to the second plurality of different types of devices, the second interface and the second bus operating at a second clock frequency that differs from the first clock frequency, wherein

the cache control of the cache system serves as a switchboard for communication between the first processor and any of the first plurality of different types of devices and between the first processor and any of the second plurality of different types of devices.

2. The integrated digital signal processor of claim 1, wherein the cache system further implements communication between the first interface and the second interface.

3. The integrated digital signal processor of claim 1, wherein the processing core further comprises a second processor, and the cache system implements communication between the second processor and the first interface and between the second processor and the second interface.

4. The integrated digital signal processor of claim 3, wherein the first processor is a general purpose processor and the second processor is a vector processor having a single-instruction-multiple-data architecture.

5. The integrated digital signal processor of claim 3, wherein the cache system implements communication between either processor and any of the first plurality of different types of devices and between either processor and any of the second plurality of different types of devices.

6. The integrated digital signal processor of claim 1, wherein the first interface further comprises a memory controller, and the second interface comprises a UART.

7. An integrated digital signal processor comprising:

a general purpose processor;

a vector processor capable of operating in parallel with the general purpose processor;

a first set of input/output devices, the first set including multiple input/output devices;

a second set of input/output devices, the second set including one or more input/output devices;

a first bus directly connected to the first set of input/output devices for data transmissions within the integrated digital signal processor;

a second bus directly connected to the second set of input/output devices for data transmissions within the integrated digital signal processor; and

a cache system coupled to the general purpose processor, the vector processor, the first bus, and the second bus, wherein the cache system is configurable to provide communications between the general purpose processor and the first set of input/output devices via the first bus, between the general purpose processor and the second set of input/output devices via the second bus, between the vector processor and the first set of input/output devices via the first bus, and between the vector processor and the second set of input/output devices via the second bus, wherein the first bus has a first bandwidth for transmission of data, and the first bandwidth is greater than a second bandwidth that the second bus provides for transmission of data, and wherein the vector processor has a third bandwidth for data that is greater than the second bandwidth, and the cache system comprises;

a cache memory; and

a data path interconnecting the cache memory, the general purpose processor, the vector processor, the first bus, and the second bus, wherein the data path lacks a connection between the vector processor and the second bus.

8. The integrated digital signal processor of claim 7, wherein communications between the vector processor and the second data bus are via the cache memory.

9. The integrated digital signal processor of claim 8, wherein the data path directly connects the vector processor to the first data bus.

10. The integrated digital signal processor of claim 7, wherein the data path directly connects the general purpose processor to the second data bus.