Method for controlling a direct mapped or two way set associative cache memory in a computer system

• US 6,425,056 B2
• Filed: 10/26/1998
• Issued: 07/23/2002
• Est. Priority Date: 10/26/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Meyer, James W.
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US09/179,236
• Publication Number:
  US 20010044872A1
• Time in Patent Office: 1,366 Days
• Field of Search: 711/128, 711/118, 711/3, 711/120, 711/129, 711/170, 711/212, 711/108, 711/154, 365/49, 713/2, 713/100
• US Class Current: 711/128
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing

Abstract

A method is described for controlling a cache memory that may be either a direct-mapped or two-way set-associative cache. The described method is performed by a configurable cache controller. The cache controller receives a configuration signal having first and second states, with the configuration signal of the first state configuring the cache controller to monitor and control a direct-mapped cache, and the configuration signal of the second state configuring the cache controller to monitor and control a two-way set-associative cache. The cache controller includes first and second comparators, each able to compare respective first and second cache tags to a memory address. Both of the comparators are enabled when monitoring cache hits to a two-way set-associative cache, whereas only one of the comparators is enabled when monitoring a direct-mapped cache. The cache controller also includes first and second control circuits, each receiving a hit signal produced by a respective one of the comparators. Thus, both of these control circuits may operate when the cache controller monitors and controls a two-way set-associative cache, while only one of the control circuits will be selectively enabled when the cache controller monitors and controls a direct-mapped cache. The two-state configuration signal may be conveniently provided by a flip-flop or other programmable element whose value is set during computer system initialization routines.

Claims

1. A method of controlling a cache memory in a computer system, comprising:

determining in which of first and second configurations the cache memory is organized during at least one of a plurality of power-on self-test and system initialization operations of the computer system;

generating a configuration signal using a configuration control circuit based on a result of the determination, the configuration signal indicating whether the cache memory is in the first or second configuration;

receiving a memory address;

transmitting the configuration signal to first and second comparators;

if the cache memory is of the first configuration, then enabling the first comparator to retrieve first tag data stored in the cache memory, and comparing the first tag data to the memory address using the first comparator; and

if the cache memory is of the second configuration, then enabling both the first and second comparators to retrieve first and second tag data, respectively, stored in the cache memory, and comparing the first and second tag data to the memory address using the first and second comparators, respectively.

2. A method according to claim 1 wherein the first tag data is compared to a first portion of the memory address, and wherein the second tag data is compared to a second portion of the memory address.

3. A method according to claim 1 wherein if the cache memory is of the second configuration, then the method further comprises retrieving the first tag data and comparing the first tag data to the memory address.

4. A method according to claim 1 wherein the first cache configuration is a direct-mapped cache configuration, and wherein the second cache configuration is a two-way set-associative cache configuration.

5. A method of controlling a cache memory in a computer system, comprising:

determining in which of first and second cache configurations the cache memory is organized from a configuration signal that is determined during at least one of a plurality of power-on self-test and system initialization operations of the computer system;

based on the configuration signal, programming a cache configuration control circuit to set a configuration control mode of a cache controller;

receiving a memory address;

transmitting the configuration control mode to first and second comparators;

if the cache memory is organized in the first configuration, then;

enabling the first comparator to retrieve first tag data stored in the cache memory at a location corresponding with the memory address; and

comparing the first tag data using the first comparator to a first associated portion of the memory address;

if the cache memory is organized in the second configuration, then;

enabling both the first and second comparators to retrieve first and second tag data, respectively, stored in the cache memory at a location corresponding with the memory address; and

comparing the first and second tag data to a second associated portion of the memory address using the first and second comparators, respectively.

6. A method according to claim 5 wherein if the cache memory is organized in the second configuration, then the method also comprises retrieving the first tag data and comparing the first tag data to the second associated portion of the memory address.

7. A method according to claim 5 wherein determining in which of first and second cache configurations the cache memory is organized includes receiving a configuration signal having one of first and second states respectively indicating the first and second cache configurations.

8. A method according to claim 5 wherein the first cache configuration is a direct-mapped cache configuration.

9. A method according to claim 5 wherein the second cache configuration is a plural-way set-associative cache configuration.

10. A method according to claim 5 wherein the first cache configuration is a direct-mapped cache configuration, and wherein the second cache configuration is a two-way set-associative cache configuration.

11. A method of controlling a cache memory in a computer system, comprising:

initiating at least one of a plurality of power-on self-test and system initialization operations of the computer system;

during at least one of the plurality of power-on self-test and system initialization operations, receiving a cache configuration signal having one of first and second states, one of the first and second states corresponding to a cache memory having a direct-mapped configuration and the other of the first and second states corresponding to a cache memory having a two-way set-associative configuration;

receiving a memory address;

if the cache memory is organized in the first configuration, then;

enabling a first comparator to retrieve first tag data stored in the cache memory at a location corresponding with the memory address; and

comparing the first tag data to a first associated portion of the memory address using the first comparator;

if the cache memory is organized in the second configuration, then;

enabling the first comparator to retrieve first tag data, and enabling a second comparator to retrieve second tag data, the first and second tag data being stored in the cache memory at a location corresponding with the memory address; and

comparing the first tag data using the first comparator, and comparing the second tag data using the second comparator, to first and second associated portions, respectively, of the memory address.

12. A method according to claim 11 wherein if the cache configuration signal has the second state, and the second tag data match the second associated portion, respectively, the method also comprises:

transmitting an hit signal from the second comparator to a second control circuit; and

applying a stored data to a data bus.

13. A method according to claim 11 wherein if the cache configuration signal has the first state, and the first tag data match the first associated portion, the method also comprises:

transmitting an hit signal from the first comparator to a first control circuit; and

applying a stored data to a data bus.

14. A method of controlling a cache memory in a computer system, comprising:

initiating at least one of a plurality of power-on self-test and system initialization operations of the computer system;

during at least one of the plurality of power-on self-test and system initialization operations, determining a cache configuration signal, the cache configuration signal having first and second states, one of the first and second states corresponding to a cache memory having a direct-mapped configuration and the other of the first and second states corresponding to a cache memory having a two-way set-associative configuration;

receiving a memory address;

if the cache configuration signal has the first state, then enabling a first comparator to retrieve first tag data stored in the cache memory at a location corresponding with the memory address;

if the cache configuration signal has the first state, then enabling the first comparator to select a first portion of the memory address;

if the cache configuration signal has the first state, then enabling the first comparator to compare the first tag data to the first portion of the memory address;

if the cache configuration signal has the second state, then enabling first and second comparators to retrieve first and second tag data stored in the cache memory at a location corresponding with the memory address;

if the cache configuration signal has the second state, then enabling first and second comparators to select first and second portions, respectively, of the memory address; and

if the cache configuration signal has the second state, then enabling the first and second comparators to compare the first and second tag data to the first and second portions, respectively, of the memory address.

15. A method according to claim 14 wherein the cache configuration signal has the first state when the cache memory is configured as a direct-mapped cache, and wherein the cache configuration signal has the second state when the cache memory is configured as a two-way set-associative cache.