Data encoder/decoder for a high speed serial link

• US 6,425,107 B1
• Filed: 10/13/2000
• Issued: 07/23/2002
• Est. Priority Date: 01/30/1997
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited, Fujitsu Network Communications Incorporated (Fujitsu Limited)
• Original Assignee: Fujitsu Limited, Fujitsu Network Communications Incorporated (Fujitsu Limited)
• Inventors: Sluyski, Michael, Strouble, Raymond L., Caldara, Stephen A.
• Primary Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US09/687,289
• Time in Patent Office: 648 Days
• Field of Search: 714/759, 714/8, 714/30, 714/726, 714/729, 714/735, 341/58, 341/59, 341/68, 341/100, 341/101, 341/106, 341/56, 341/69, 341/73, 341/75, 341/94-95, 375/240, 375/292, 703/13, 703/21, 710/20, 710/72, 358/261.4, 717/1, 717/10, 704/503
• US Class Current: 714/759
• CPC Class Codes: G06T 9/005 Statistical coding, e.g. Huffman, run length coding
• CPC Class Codes: H03M 13/31 combining coding for error detection or correction and efficient use of the spectrum without error detection or correction H03M5/14 , H03M5/145
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof

Abstract

An encoder/decoder is disclosed which is operative to convert an 8 bit value to a ten bit serial run length limited code for transmission over a serial data link. The encoding technique maintains DC balance within 2 bits over a single ten bit word and compensates for DC imbalance by inverting selected words in the transmission sequence to correct for a DC imbalance resulting from the transmission of a prior unbalanced word. One or more encoding lookup tables are employed at the encoder to map each byte into a ten bit run length limited code for serialization and transmission over the serial data link. A second decoding lookup table is employed at the decoder to map the received 10 bit run length limited code into the original 8 bit value.

Claims

1. Encoding apparatus for converting a plurality of input values to a corresponding plurality of run length limited codes, wherein each of said input values comprises a plurality of bits, said encoding apparatus comprising:

a map for mapping said plurality of input values into said corresponding plurality of run length limited codes, wherein each one of said corresponding plurality of run length limited codes is either DC balanced or imbalanced in the same direction by the same magnitude, said map being indexed by said plurality of input values and operative to produce a single one of said run length limited codes as a map output in response to the input of each one of said plurality of input values, wherein a single bit within a predetermined bit position of each one of said plurality of input values comprises a imbalance indicator bit having a first imbalance state or a second imbalance state, said run length limited codes being stored within said map such that each of said plurality of run length limited codes are imbalanced for input values having said imbalance indicator bit of said first imbalance state and balanced for input values having said imbalance indicator bit of said second imbalance state.

2. The encoding apparatus of claim 1, said apparatus further comprising:

a DC balance controller, said controller receiving as an input said imbalance indicator bit, said DC balance controller being operative to produce an output signal having a first output state in the event that said run length limited codes previously output from said map for a given frame are cumulatively imbalanced and the imbalance indicator bit for the current input value to said map is of said first imbalance state, said DC balance controller otherwise being operative to produce an output signal having a second output state;

a conditional inverter in electrical communication with said map and operative to receive as inputs to said inverter said run length limited codes output from said map, said conditional inverter receiving said DC balance controller output signal and operative in response to detection of said DC balance controller output signal of said first output state to invert the respective run length limited code received by said conditional inverter.

3. The encoding apparatus of claim 2 wherein said map comprises a lookup table having a plurality of lookup table locations and each of said run length limited codes is stored within one of said locations within said lookup table, said locations being indexed by said input values.

4. The encoding apparatus of claim 3 wherein said balanced Run length limited codes are selectively stored in a first plurality of said lookup table locations and said imbalanced Run length limited codes are selectively stored in a second plurality of said lookup table locations.

5. The encoding apparatus of claim 2 wherein said conditional inverter is operative to pass the respective run length limited code through the conditional inverter in a non-inverted form in the event said DC balance controller output, signal is in said second state.

6. The encoding apparatus of claim 5 wherein said DC balance controller provides said output signal of said second output state responsive to receipt of an imbalance indicator bit of said second imbalance state.

7. The encoding apparatus of claim 5 wherein said DC balance controller includes a prior balance state indicator having a first indicator state when the Run length limited codes previously output from said map for a frame are collectively balanced and a second indicator state when said Run length limited codes previously output from said map for said frame are collectively imbalanced.

8. The encoding apparatus of claim 7 wherein said DC balance controller is operative to produce an output signal of said second output state in the event:

(a) said prior state balance indicator is of said first indicator state and said imbalance indicator bit for the current input value is of said second imbalance state;

(b) said prior state balance indicator is of said second indicator state and said imbalance indicator bit for the current input value is of said second imbalance state;

or

(c) said prior state balance indicator is of said first indicator state and said imbalance indicator bit for the current input value is of said first imbalance state.

9. The encoding apparatus of claim 1 wherein said imbalance indicator bit comprises the least significant bit of each one of said plurality of input values.

10. The encoding apparatus of claim 1 wherein said input values comprise eight bit input values.

11. The encoding apparatus of claim 10 wherein said Run length limited codes stored within said lookup table comprise ten bit Run length limited codes.

12. The encoding apparatus of claim 11 wherein said Run length limited codes have a maximum run length of five binary digits including the run length over successive Run length limited code boundaries.

13. The encoding apparatus of claim 1 wherein each of said Run length limited codes is balanced or imbalanced by two binary values.

14. The encoding apparatus of claim 1 wherein each of said imbalanced Run length limited codes has two more ones than zeros within the respective Run length limited code.

15. The encoding apparatus of claim 1 wherein each of said imbalanced Run length limited codes has two more zeroes than ones within the respective Run length limited code.

16. A method for maintaining DC balance on a serial data link comprising the steps of:

transmitting a packet over a serial data link comprising a plurality of run length limited codes and an offset correction field;

determining whether said transmitted run length limited codes are cumulatively balanced;

transmitting a first value in the offset correction field which is DC balanced in the event said determining step reveals that said transmitted run length limited codes are cumulatively DC balanced; and

transmitting a second value in the offset correction field which is selected to cause the packet to be DC balanced following transmission of said offset correction field in the event said determining step reveals that said transmitted run length limited codes are cumulatively DC imbalanced.