High level automatic core configuration

• US 6,425,109 B1
• Filed: 07/23/1999
• Issued: 07/23/2002
• Est. Priority Date: 07/23/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Tetreault, Scott Alan, Ventrone, Sebastian Theodore, Dean, Alvar Antonio, Choukalos, Charles N.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US09/360,384
• Time in Patent Office: 1,096 Days
• Field of Search: 715/1, 715/8, 715/11, 715/18, 713/1
• US Class Current: 716/119
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A system and method for interconnecting a plurality of cores into a single functional core. The method involves creating for each core a pin configuration structure based on a set of configuration rules. When the cores to be interconnected are selected, the pin configuration structure is accessed by the configurator program tool of the present invention. The configurator program tool then connects the cores together using the pin configuration structure and configuration rules for the selected cores. The configurator program tool generates an error-free high level model of the interconnected cores. The configurator program tool allows configuration flexibility and is general enough to handle most configuration scenarios. The tool is also easy to code, extensible, and can be applied to existing core designs with no modification of the cores themselves.

Claims

1. A method of creating a system of interconnected cores, comprising the steps of:

creating for each core a pin configuration structure based on a set of pin configuration rules;

selecting a plurality of cores to be interconnected;

accessing the pin configuration structure for the cores selected; and

connecting the cores using a connectivity program based on the pin configuration structure and configuration rules for the selected cores.

2. The method of claim 1, further comprising the steps of:

determining a fanout limit for each pin of the cores; and

connecting the cores in a multiple fanout configuration using the connectivity program to ensure that an acceptable number of fanout connections is not exceeded.

3. The method of claim 1, further comprising the steps of:

determining for each pin of the cores whether the pin is part of a group of related pins; and

using the connectivity program to match each group of related pins together when connecting the cores.

4. The method of claim 1, further comprising the step of:

initializing the connectivity program by choosing a set of cores to be connected together, flagging external pins on the cores, and loading descriptive files containing the pin configuration structure and configuration rules.

5. The method of claim 1, further comprising the step of creating a high-level source that contains information about the system of interconnected cores created.

6. The method according to claim 5, further comprising the step of performing a logical verification based on said source.

7. The method of claim 1, wherein said cores comprise a plurality of chiplets, and said connectivity program connects said chiplets into a single functional core.

8. A computer system comprising:

a central processing unit;

a bus;

computer system memory, said computer system memory being connected to said central processing unit via said bus; and

a configurator tool stored in said computer system memory and executable on said central processing unit, said configurator tool being operable to create a system of interconnected cores based on a pin configuration structure and a set of configuration rules for the cores.

9. The computer system according to claim 8, wherein said configurator tool further comprises:

a tool for accessing a pin configuration structure and a set of configuration rules for the cores; and

a tool for connecting the cores together based on the pin configuration structure and the configuration rules.

10. The computer system according to claim 8, wherein said configurator tool further comprises:

a tool for determining a fanout limit for each pin of the cores; and

a tool connecting the cores in a multiple fanout configuration while ensuring that the fanout limit is not exceeded.

11. The computer system according to claim 8, wherein said configurator tool further comprises:

a tool for determining for each pin of the cores whether the pin is part of a group of related pins; and

a tool for matching each group of related pins together when connecting the cores.

12. The computer system according to claim 8, wherein said configurator tool further comprises a tool for creating a high-level source that contains information about the system of interconnected cores created.

13. A computer-readable medium having computer-executable instructions for creating a system of interconnected cores by performing steps comprising:

accessing a pin configuration structure and a set of configuration rules for the cores; and

connecting the cores together based on the pin configuration structure and the configuration rules.

14. The computer-readable medium of claim 13, wherein said steps performed by the computer-executable instructions further comprise the steps of:

determining a fanout limit for each pin of the cores; and

connecting the cores in a multiple fanout configuration while ensuring that the fanout limit is not exceeded.

15. The computer-readable medium of claim 13, wherein said steps performed by the computer-executable instructions further comprise the steps of:

determining for each pin of the cores whether the pin is part of a group of related pins; and

matching each group of related pins together when connecting the cores.

16. The computer-readable medium of claim 13, wherein said steps performed by the computer-executable instructions further comprise the step of creating a high-level source that contains information about the system of interconnected cores created.

17. The computer-readable medium of claim 16, wherein said steps performed by the computer-executable instructions further comprise the step of performing a logical verification based on said high level source.