Fabrication of a high density long channel DRAM gate with or without a grooved gate

• US 6,426,175 B2
• Filed: 02/22/1999
• Issued: 07/30/2002
• Est. Priority Date: 02/22/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hakey, Mark C., Holmes, Stevn J., Furukawa, Toshiharu, Horak, David V., Rabidoux, Paul A.
• Primary Examiner(s): Huff, Mark F.
• Assistant Examiner(s): Mohamedulla, Saleha R.
• Application Number:
  US09/253,455
• Publication Number:
  US 20010003034A1
• Time in Patent Office: 1,254 Days
• Field of Search: 430/312, 430/313, 430/314, 430/319, 430/316, 430/317, 430/5, 438/197, 438/199, 438/257, 438/259, 438/270, 438/284, 438/695, 438/696, 438/700, 438/701, 438/702, 438/703
• US Class Current: 430/313
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

The present invention lengthens gate conductors used in memory chips to limit leakage current, while still allowing the overall size of cells to remain the same. The channel length for each gate is increased by decreasing the size of spaces between gates. Decreases in space size occurs by using photolithographic image enhancement techniques. These techniques allow the space between gate conductors to be smaller while the gate size increases. In addition, a groove may be added that additionally lengthens the effective channel length and provides an additional electrical shield to limit leakage current. These techniques lead to the same density memory cells for a given process with less leakage. Finally, if grooved gate structures are used, having a longer gate conductor allows a three sigma process to be used, which increases yields.

Claims

1. A method for forming a transistor in a memory device, the method comprising the steps of:

a) forming a gate stack layer on a substrate;

b) patterning the gate stack layer to simultaneously define a gate and two spaces from a single image, with the gate situated between the two spaces to form a space/line/space combination, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space; and

c) forming first and second source/drain regions in the substrate on opposite sides of the gate.

2. The method of claim 1 wherein the gate stack layer further comprises an insulating layer and wherein the step of patterning the gate stack layer to simultaneously define a gate and two spaces from a single image, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space, further comprises the step of forming sidewall spacers on the insulating layer to reduce widths of the two spaces, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space.

3. The method of claim 1 wherein the step of forming a gate stack layer on a substrate comprises the steps of:

i) forming in the substrate a groove having a width that is smaller than the gate;

ii) forming an insulating layer over the substrate; and

iii) depositing the gate stack layer.

4. The method of claim 3 wherein the step of forming in the substrate a groove having a width that is smaller than the gate comprises forming the groove by using hybrid photoresist.

5. The method of claim 1 further comprising the step of forming a deep trench capacitor in the substrate such that the deep trench capacitor has a storage electrode electrically connected to one of the first and second source/drain regions.

6. The method of claim 5 further comprising forming a bit line that is electrically connected to the other of the first and second source/drain regions.

7. The method of claim 1 wherein the step of patterning the gate stack layer to simultaneously define a gate and two spaces from a single image, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space, comprises the step of using hybrid photoresist to define the gate and the two spaces, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space.

8. The method of claim 1 wherein the gate stack layer further comprises an insulating layer and wherein the step of patterning the gate stack layer to simultaneously define a gate and two spaces from a single image, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space, comprises the steps of:

i) depositing a hybrid photoresist layer onto the gate stack layer;

ii) exposing the hybrid photoresist layer through a mask comprising a shape such that first portions of the hybrid photoresist are exposed to a high exposure level, second portions of the hybrid photoresist are exposed to a medium exposure level, and third portions of the hybrid photoresist are exposed to a low exposure level;

iii) developing the hybrid photoresist layer such that the second portions of the hybrid photoresist are removed, the removal of the second portions exposing two regions of the insulating layer;

iv) etching the insulating layer;

v) forming spacers over sidewalls of the insulating layer to reduce widths of the two regions of the insulating layer; and

vi) etching the two regions of the insulating layer to form the two spaces, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space.

9. The method of claim 8 wherein the step of developing the hybrid photoresist layer further exposes at least one loop, wherein the substrate further comprises a gate area in which the two regions of the insulating layer are formed and at least one support area in which the at least one loop is formed, and wherein the method, after the step of exposing the hybrid photoresist layer but before the step of developing the hybrid photoresist layer, further comprises the step of blanket exposing the at least one support area with at least an intermediate light energy capable of making the hybrid resist that is exposed in this step soluble to developer in the step of developing the hybrid photoresist layer.

10. The method of claim 1 wherein the step of patterning the gate stack layer to simultaneously define a gate and two spaces from a single image, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space, comprises the steps of:

i) depositing a hybrid photoresist layer onto the gate stack layer;

ii) exposing the hybrid photoresist layer through a mask comprising a shape such that first portions of the hybrid photoresist are exposed to a high exposure level, second portions of the hybrid photoresist are exposed to a medium exposure level, and third portions of the hybrid photoresist are exposed to a low exposure level;

iii) developing the hybrid photoresist layer such that the second portions of the hybrid photoresist are removed, the removal of the second portions exposing two regions of the gate stack layer; and

iv) etching the two regions of the gate stack layer to form the two spaces, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space.

11. A The method of claim 1 wherein the step of patterning the gate stack layer to simultaneously define a gate and two spaces from a single image, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space, comprises the steps of:

i) depositing a negative photoresist layer onto the gate stack layer;

ii) exposing the negative photoresist layer to define two regions of the negative photoresist layer;

iii) developing the negative photoresist layer to expose two regions of the gate stack layer;

iv) forming spacers over sidewalls of the negative photoresist layer to reduce widths of the two regions; and

v) etching the two regions of the gate stack layer to form the two spaces, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space.

12. The method of claim 11 wherein the gate stack layer further comprises an insulating layer that is beneath the negative photoresist layer, wherein the step of developing the negative photoresist layer further exposes at least one loop, wherein the substrate further comprises a gate area in which the two regions of the gate stack layer are formed and at least one support area in which the at least one loop is formed, and wherein the step of etching the two regions of the gate stack layer to form the two spaces, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space, further comprises the steps of:

i) removing the negative layer of photoresist;

ii) etching through at least part of the insulating layer to create a hard mask;

ii) depositing a second layer of photoresist onto the gate stack layer;

iv) patterning the second layer of photoresist to create a trim mask in the at least one support area, the trim mask exposing the at least one loop;

v) etching a gate stack area in the trim mask to remove the at least one loop;

vi) removing the second layer of photoresist; and

vii) etching the gate stack layer using the hard mask.

13. The method of claim 1 wherein the gate stack layer further comprises an insulating layer and wherein the step of patterning the gate stack layer to simultaneously define a gate and two spaces from a single image, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space, comprises the steps of:

i) depositing a negative photoresist layer onto the gate stack layer;

ii) exposing the negative photoresist layer to define two regions of the negative resist layer;

iii) developing the negative photoresist layer to expose two regions of the insulating layer;

iv) etching the insulating layer;

v) forming spacers over sidewalls of the insulating layer to reduce widths of the two regions of the insulating layer; and

vi) etching the two regions of the insulating layer to form the two spaces, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space.

14. The method of claim 1 wherein the step of patterning the gate stack layer to simultaneously define a gate and two spaces from a single image, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space, comprises the steps of:

i) depositing a negative photoresist layer onto the gate stack layer;

ii) exposing the negative photoresist layer through a mask comprising a first region that abuts a second region that also abuts a third region, wherein the first region and the third region are at a first phase and the second region is at a second phase that is about 180 degrees from the first phase, such that light that has passed through the second region will be about 180 degrees out of phase with light that has passed through the first and third regions, and wherein first portions of the negative photoresist are exposed to a high exposure level, and second portions of the negative photoresist are exposed to a low exposure level, the low exposure level occurring under the abutment of the first and second source/drain regions and the abutment of the second and third regions;

iii) developing the negative photoresist layer such that the second portions of the negative photoresist are removed, the removal of the second portions exposing two regions of the gate stack layer;

iv) forming spacers over sidewalls of the negative photoresist layer to reduce widths of the two regions; and

v) etching the two regions of the gate stack layer to form the two spaces, with the gate situated between the two spaces, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space.

15. A method for forming a transistor in a memory device, the method comprising the steps of:

a) forming a gate stack layer on a substrate;

b) patterning the gate stack layer to simultaneously define a gate and two spaces from a single image, the step of patterning the gate stack layer comprising the steps of;

i) depositing a negative photoresist layer onto the gate stack layer;

ii) exposing the negative photoresist layer to define two regions of the negative photoresist layer;

iii) developing the negative photoresist layer to expose two regions of the gate stack layer; and

iv) etching the two regions of the gate stack layer to form the two spaces, with the gate situated between the two spaces to form a space/line/space combination, the gate and one of the two spaces having a total width that is approximately 2.0 F, wherein the gate has a width that is at least twice a width of the one space; and

c) forming first and second source/drain regions in the substrate on opposite sides of the gate.

16. The method of claim 15 further comprising the step of forming a deep trench capacitor in the substrate such that the deep trench capacitor has a storage electrode electrically connected to one of the first and second source/drain regions.

17. The method of claim 16 further comprising the step of forming a bit line that is electrically connected to the other of the first and second source/drain regions.

18. The method of claim 15 wherein the step of forming a gate stack layer on a substrate comprises the steps of:

i) forming in the substrate a groove having a width that is smaller than the gate;

ii) forming an insulating layer over the substrate; and

iii) depositing the gate stack layer.

19. The method of claim 18 wherein the step of forming in the substrate a groove having a width that is smaller than the gate comprises forming the groove by using hybrid photoresist.