Flash memory and manufacturing method therefor

• US 6,426,257 B1
• Filed: 04/19/2000
• Issued: 07/30/2002
• Est. Priority Date: 01/07/1998
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Kanamori, Kohji
• Primary Examiner(s): Nguyen, Tuan H.
• Assistant Examiner(s): CHEN, JACK S J
• Application Number:
  US09/552,226
• Time in Patent Office: 832 Days
• Field of Search: 438/266, 438/257, 438/258, 438/259, 438/261, 438/262, 438/263, 438/264, 438/265, 438/593
• US Class Current: 438/266
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In a flash memory that has a floating gate, a control gate, and an erase gate that are all mutually insulated, in which data erasing is performed by extracting electrons from the corner edge of the floating gate to the erase gate via an insulation film, the insulation film between the floating gate and the erase gate is formed so as to have a uniform thickness at its corner part.

Claims

1. A method of manufacturing a flash memory which is provided with a floating gate, a control gate, and an erase gate, each of said floating gate, said control gate and said erase gate being mutually insulated from one another, in which erasing of data is performed by extracting electrons from an edge of a corner of said floating gate via an insulation film, into said erase gate, said method comprising the steps of:

forming said float gate which is made of polysilicon and exposing a corner surface of said floating gate;

forming a silicon oxide layer on said floating gate having a uniform thickness at the corner surface of said floating gate, using a CVD process; and

forming a silicon thermal oxide film after said forming of said silicon oxide layer on said floating gate using a CVD process.

2. A method of manufacturing a flash memory according to claim 1, further comprising a step of performing thermal oxidation in an oxidizing atmosphere that includes a nitrogen compound, after said step of forming a silicon oxide layer on the floating gate, using a CVD process.

3. The method of claim 1, wherein said corner surface is a curved part having a uniform thickness at a corner of said floating gate.

4. The method of claim 3, wherein said curved part is at a uniform distance from said floating gate.

5. A method of manufacturing a flash memory which is provided with a floating gate, a control gate, and an erase gate, each of said floating gate, said control gate and said erase gate being mutually insulated from one another, in which erasing of data is performed by extracting electrons from an edge of a corner of said floating gate via an insulation film, into said erase gate, said method comprising the steps of:

forming said float gate which is made of polysilicon and exposing a corner surface of said floating gate;

forming a silicon oxide layer on said floating gate having a uniform thickness at the corner surface of said floating gate, using a CVD process; and

performing thermal oxidation in an oxidizing atmosphere that includes a nitrogen compound, after said forming of said silicon oxide film on said floating gate using a CVD process.

6. The method of claim 5, wherein said silicon oxide layer at said corner surface forms a curved part that is at a uniform distance from said floating gate.

7. The method of claim 6, wherein said curved part has a top portion opposite said floating gate approximating a quarter circle having a center which is a corner of said floating gate opposite said top portion.