Switching speed improvement in DMO by implanting lightly doped region under gate

• US 6,426,260 B1
• Filed: 09/05/2000
• Issued: 07/30/2002
• Est. Priority Date: 12/02/1997
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: MagePower Semiconductor Corporation
• Inventors: Hshieh, Fwu-Iuan
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/655,165
• Time in Patent Office: 693 Days
• Field of Search: 438/138, 438/212, 438/268, 438/270, 438/289, 438/290, 438/589
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The preset invention discloses an improved method for fabricating a MOSFET transistor on a substrate to improve the device ruggedness. The fabrication method includes the steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate and then growing an gate oxide layer over the epi-layer; (b) depositing an overlaying polysilicon layer thereon and applying a polysilicon mask for etching the polysilicon layer to define a plurality of polysilicon gates; (c) removing the polysilicon mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; (d) performing a high-energy body-conductivity-type-dopant implant, eg., boron implant, to form a plurality of shallow low-concentration regions of source-conductivity-type, e.g., n-regions, under each of e gates. A DMOS power device with improved switching speed is provided with reduced gate-to-drain capacitance without causing an increase in either the on-resistance of the threshold voltage.

Claims

1. A method for fabricating a DMOS transistor on a substrate comprising:

(a) forming an epitaxial-layer of a first conductivity type on said substrate functioning as a drain region, and then growing an gate oxide layer over said epitaxial layer;

(b) depositing an overlaying polysilicon layer and applying a polysilicon mask for etching said polysilicon layer to define a plurality of polysilicon gates;

(c) removing said polysilicon mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; and

(d) performing a high-energy light-dose body-conductivity-type dopant implant through said polysilicon gate to form a plurality of shallow low-concentration first-conductivity-type regions under each of said gates having a lower dopant concentration of said first conductivity type than said epitaxial layer.

2. The method for fabricating said DMOS transistor of claim 1 further comprising:

(e) applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type followed by removing said source blocking mask and performing a source diffusion process; and

(f) forming an overlying insulation layer covering said DMOS device followed by applying a contact mask to open a plurality of contact openings there-through.

3. The method for fabricating said DMOS transistor of claim 1 further comprising a step of:

(g) performing a low energy body-conductivity-type dopant implant to form a shallow high-concentration body-conductivity-type dopant region followed by applying a high temperature process for densification of said insulation layer and for activating a diffusion of said shallow high-concentration body-conductivity-type dopant regions.

4. The method for fabricating said MOSFET transistor of claim 1 wherein:

said step (d) is a step of applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type; and

said step (e) is a step of performing a high-energy light-dose second-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates followed by removing said source-blocking mask and performing a source diffusion process.

5. The method for fabricating said MOSFET transistor of claim 1 wherein:

said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions shallower than said source regions.

6. The method for fabricating said MOSFET transistor of claim 3 wherein:

said step (e) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions shallower than said source regions.

7. The method for fabricating said MOSFET transistor of claim 1 wherein:

said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of implanting a plurality boron ions as second-conductivity-type dopant of said second conductivity type with an energy ranging from 200 to 400 Kev.

8. The method for fabricating said MOSFET transistor of claim 1 wherein:

said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions with a depth less than 0.4 micrometers.

15. The method for fabricating said DMOS transistor of claim 1 further comprising:

e) forming an overlying insulation layer covering a top surface said DMOS device followed by applying a contact mask to open a plurality of contact openings there-through.

16. The method for fabricating said DMOS transistor of claim 15 further comprising a step of:

f) performing a low energy body-conductivity-type dopant implant to form a shallow high-concentration body-conductivity-type dopant region followed by applying a high temperature process for densification of said insulation layer and for activating a diffusion of said shallow high-concentration body-conductivity-type dopant regions.

9. A method for fabricating a trench DMOS transistor on a substrate comprising steps of:

(a) forming an epi-layer of a first conductivity type in said substrate with a bottom surface functioning as a drain;

(b) performing a body implant of a second conductivity type followed by performing a body diffusion for forming a body regions;

(c) applying a trench mask for etching a plurality of trenches in said substrate;

(d) implanting a low-energy second-conductivity-type dopant through said trenches to form a plurality of shallow-and-narrow low-concentration first-conductivity-type regions under each of said trenches;

(e) depositing a polysilicon layer to fill said trenches and etching for removing said polysilicon layer from above said top surface of said substrate to form a plurality of trenched gates;

(f) applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type followed by removing said source blocking mask and carrying out a source diffusion process; and

(g) forming an overlying insulation layer covering said DMOS device followed by applying a contact mask to open a plurality of contact openings there-through.

10. The method for fabricating said trench DMOS transistor of claim 9 further comprising a step:

(h) performing a high energy second-conductivity-type dopant implant to form a self-aligned deep high concentration second-conductivity-type dopant region below each of said source regions.

11. The method for fabricating said MOSFET transistor of claim 9 wherein:

said step (d) of forming said plurality of shallow-and-narrow low-concentration first-conductivity-type regions under each of said trenches is a step of forming said shallow-and-narrow low-concentration source-dopant regions with a region-width narrower than each of said trenches.

12. The method for fabricating said trench DMOS transistor of claim 9 wherein:

said step (d) of implanting said low-energy second-conductivity-type dopant through said trenches to form a plurality of shallow-and-narrow low-concentration first-conductivity-type regions under each of said trenches is a step of implanting a plurality boron ions as second-conductivity-type dopant with an energy ranging from 20 to 80 Kev.

13. The method for fabricating said MOSFET transistor of claim 9 wherein:

said step (d) of implanting said low-energy second-conductivity-type dopant through said trenches to form a plurality of shallow-and-narrow low-concentration first-conductivity-type regions under each of said trenches is a step of forming said shallow-and-narrow low-concentration source-dopant regions with a depth less than 0.4 micrometers below each of said trenches.

14. A method for fabricating a DMOS transistor on a substrate comprising:

a)forming an epitaxial-layer of a first conductivity type on said substrate functioning as a drain region, and then growing an gate oxide layer over said epitaxial layer;

b) depositing an overlaying polysilicon layer and applying a polysilicon mask for etching said polysilicon layer to define a plurality of polysilicon gates;

c) applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type; and

d) performing a high-energy light-dose second-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates followed by removing said source-blocking mask and performing a source diffusion process.

17. The method for fabricating said MOSFET transistor of claim 14 wherein:

said step (c) is a step of removing said polysilicon mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; and

said step (d) is a step of performing a high-energy light-dose body-conductivity-type dopant implant through said polysilicon gate to form a plurality of shallow low-concentration first-conductivity-type regions under each of said gates having a lower dopant concentration of said fist conductivity type than said epitaxial layer.

18. The method for fabricating said MOSFET transistor of claim 14 wherein:

said step (e) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions shallower than said source regions.

19. The method for fabricating said MOSFET transistor of claim 17 wherein:

said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions shallower than said source regions.

20. The method for fabricating said MOSFET transistor of claim 14 wherein:

said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of implanting a plurality boron ions as second-conductivity-type dopant of said second conductivity type with an energy ranging from 200 to 400 Kev.

21. The method for fabricating said MOSFET transistor of claim 14 wherein:

said step (d) of performing a high-energy light-dose body-conductivity-type dopant implant to form a plurality of shallow low-concentration source-conductivity-type regions under each of said gates is a step of forming said shallow low-concentration source-conductivity-type regions with a depth less than 0.4 micrometers.