Method of forming solder bumps on a semiconductor wafer

• US 6,426,282 B1
• Filed: 05/04/2000
• Issued: 07/30/2002
• Est. Priority Date: 05/04/2000
• Status: Expired due to Term

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Yang, Lisa L., Athreya, Shankarram, Ngan, Kenny King-Tai, Saigal, Dinesh
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/565,569
• Time in Patent Office: 817 Days
• Field of Search: 438/106, 438/113, 438/613, 438/614, 438/639, 438/653, 438/710, 438/14, 438/17, 438/107, 257/676, 257/766, 257/770, 257/776, 257/748, 257/779
• US Class Current: 438/613
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13686 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/1369 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method of forming solder bumps on a semiconductor wafer utilizing a low temperature biasable electrostatic chuck. In particular, the method comprises the steps of providing at least one bond pad on the semiconductor wafer, forming a barrier layer over the bond pad, and forming the solder bumps upon the at least one bond pad. By controlling the temperature and biasing of the electrostatic chuck, the barrier layer, such as nickel vanadium, exhibits a low tensile or compressive stress.

Claims

1. A method of forming solder bumps on a semiconductor wafer comprising the steps of:

providing at least one bond pad on the semiconductor wafer;

forming a barrier layer over said at least one bond pad; and

forming said solder bumps upon said barrier layer wherein the barrier layer has a low tensile or compressive stress.

2. The method of claim 1 further comprising the steps of sputtering said semiconductor wafer with an adhesive layer over said at least one bond pad and prior to said forming said barrier layer.

3. The method of claim 1 further comprising the steps of reflowing said solder to form a solder bump upon said bond pad.

4. The method of claim 2 further comprising the steps of:

depositing a layer of silicon nitride over said at least one bond pad;

depositing a polyimide layer over said silicon nitride layer;

etching at least one channel through said silicon nitride and polyimide layers to expose said at least one bond pad; and

depositing said adhesive layer on said exposed at least one bond pad and within said at least one channel.

5. The method of claim 2 wherein said adhesive layer is titanium.

6. The method of claim 1 wherein said barrier layer is nickel vanadium.

7. The method of claim 1 wherein said forming steps are performed on a low temperature biasable electrostatic chuck.

8. The method of claim 7 wherein said temperature and biasing of said electrostatic chuck are selected to achieve said low tensile or compressive strength film.

9. The method of claim 8 wherein the temperature of said electrostatic chuck is in the range of 25 degrees Celsius to 200 degrees Celsius.

10. The method of claim 8 wherein the biasing power of said electrostatic chuck is in the range of 50 Watts to 800 Watts.

25. The method of claim 8 wherein the operating bias power of said electrostatic chuck is in the range of 50 Watts to 800 Watts.

11. A method of forming solder bumps on a semiconductor wafer in a semiconductor wafer process chamber having an electrostatic chuck, comprising the steps of:

selecting an operating temperature of said electrostatic chuck in the range of 25 degrees Celsius to 200 degrees Celsius;

selecting an operating bias power of said electrostatic chuck in the range of 50 Watts to 800 Watts;

sputtering said semiconductor wafer with a barrier deposition material to form a layer over at least one solder pad of said semiconductor wafer; and

depositing solder on said barrier layer.

12. The method of claim 11 further comprising the step of sputtering said semiconductor wafer with an adhesive layer prior to said sputtering step of said barrier layer.

13. The method of claim 11 further comprising the step of reflowing said solder to form a solder bump upon said barrier layer.

14. The method of claim 12 further comprising the steps of:

depositing a layer of silicon nitride over said at least one bond pad;

depositing a polyimide over said silicon nitride layer;

etching at least one channel through said silicon nitride and polyimide layers to expose said at least one bond pad; and

depositing said adhesive layer on said exposed at least one bond pad and within said at least one channel.

15. The method of claim 12 wherein said adhesive layer is titanium.

16. The method of claim 11 wherein said barrier layer is nickel vanadium.

17. The method of claim 11 wherein the temperature of said electrostatic chuck is in the range of 50 degrees Celsius to 100 degrees Celsius.

18. The method of claim 11 wherein the biasing power of said electrostatic chuck is in the range of 300 Watts to 400 Watts.

19. In a system for controlling the process sequence of wafers through a chamber having a low temperature biasable electrostatic chuck, a computer readable medium in a general purpose computer system that operates a special purpose controller when executing a deposition program for said chamber to perform a process comprising the steps of:

selecting an operating temperature of said electrostatic chuck in the range of 25 degrees Celsius to 200 degrees Celsius;

selecting an operating bias power of said electrostatic chuck in the range of 50 Watts to 800 Watts;

sputtering said semiconductor wafer with a barrier deposition material to form a layer over at least one solder pad of said semiconductor wafer; and

depositing solder on said barrier layer.

20. The method of claim 19 further comprising the step of sputtering said semiconductor wafer with an adhesive layer prior to said sputtering step of said barrier layer.

21. The method of claim 19 further comprising the step of reflowing said solder to form a solder bump upon said barrier layer.

22. The method of claim 20 further comprising the steps of:

depositing a layer of silicon nitride over said at least one bond pad;

depositing a polyimide over said silicon nitride layer;

etching at least one channel through said silicon nitride and polyimide layers to expose said at least one bond pad; and

depositing said adhesive layer on said exposed at least one bond pad and within said at least one channel.

23. The method of claim 19 wherein the temperature of said electrostatic chuck is in the range of 50 degrees Celsius to 100 degrees Celsius.

24. The method of claim 19 wherein the biasing power of said electrostatic chuck is in the range of 300 Watts to 400 Watts.