Circuit board

• US 6,426,468 B1
• Filed: 09/19/2000
• Issued: 07/30/2002
• Est. Priority Date: 02/14/1997
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Eastern
• Original Assignee: Kabushiki Kaisha Eastern
• Inventors: Tanaka, Tadahisa, Utsunomiya, Hisanobu
• Primary Examiner(s): PALADINI, ALBERT WILLIAM
• Application Number:
  US09/664,793
• Time in Patent Office: 679 Days
• Field of Search: 174/255, 174/261, 174/262, 361/800, 361/816, 361/111, 439/608, 439/88, 439/126
• US Class Current: 174/261
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The circuit board of the present invention makes the length of the conductor patterns shorter and improves the electric performance for the high speed signal processing. The circuit board of the present invention, which comprises a substrate, is characterized in that the substrate includes: a first face on which conductor patterns, which will be connected to a semiconductor chip, are formed; a second face on which a plurality of pads, on which terminals are formed, are matrically formed; and plated through holes whose one end are respectively opened in the conductor patterns and whose the other ends are respectively opened in the pads, wherein inner faces of the plated through holes are coated with plating layers so as to respectively electrically connect the conductor patterns with the pad.

Claims

1. A circuit board comprising a substrate for connecting to a semiconductor chip comprising:

a plurality of plated through holes, each through hole having an upper end and a lower end, extending through said substrate;

wherein said substrate has a first face and a second face;

wherein said first face has a plurality of conductor patterns formed thereon for connecting to said semiconductor chip;

wherein said conductor patterns include a plurality of adjacent clock lines;

a first metallic shield layer formed on said first face between said adjacent clock lines;

a ground line connected with said first metallic shield layer;

a plurality of terminals formed on a plurality of matrically formed lands formed on said second face;

a plurality of second metallic shield layers which respectively enclose said lands; and

wherein said upper ends of said through holes are directly connected to said conductor patterns, and said lower ends of said through holes are directly connected to said lands; and

wherein said plated through holes each have inner faces coated with plating layers in order to electrically connect said conductor patterns with said lands.

2. The circuit board according to claim 1, comprising a plurality of connecting sections for connecting to said semiconductor chip, wherein said conductor patterns linearly connect said connecting sections with said one ends of said through holes.

3. The circuit board according to claim 1, wherein said terminals are solder balls on said lands.

4. A circuit board for connecting to a semiconductor chip comprising:

a substrate for connecting to the semiconductor chip, said substrate having a first face and a second face;

a plurality of plated through holes extending through said substrate, each through hole having an upper end and a lower end;

wherein said first face has a plurality of conductor patterns formed thereon for connecting to said semiconductor chip and said second face does not have conductor patterns formed thereon for connecting to said semiconductor chip;

a plurality of adjacent clock line conductor patterns;

a first metallic shield layer formed between said adjacent clock lines on said first face;

a ground line connected with said first metallic shield layer;

a plurality of terminals formed on a plurality of matrically formed lands formed on said second face;

a plurality of second metallic shield layers which respectively enclose said lands; and

wherein said upper ends of said through holes open into said conductor pattern, and said lower ends of said through holes open into said lands; and

wherein said plated through holes each have inner faces coated with plating layers in order to electrically connect said conductor patterns with said lands.

5. The circuit board according to claim 4, said substrate further comprising:

conductor patterns for shielding;

a ground plane; and

said conductor patterns for shielding are connected to said ground plane;

wherein said conductor patterns for shielding are positioned close to said conductor patterns for clock signals.

6. The circuit board according to claim 4, wherein said conductor patterns have connecting sections for connecting to said semiconductor chip;

and

said one ends of said plated through holes are linearly connected with said connecting sections of said conductor patterns.