Printed board with signal wiring patterns that can measure characteristic impedance

• US 6,426,469 B2
• Filed: 01/30/2001
• Issued: 07/30/2002
• Est. Priority Date: 01/31/2000
• Status: Expired due to Fees

• Current Assignee: Ajinomoto Co., Inc., Victor Company of Japan Limited (JVC Kenwood Corporation), Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Ajinomoto Co., Inc., Victor Company of Japan Limited (JVC Kenwood Corporation), Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Deguchi, Takahiro, Koga, Yuichi, Nakamura, Shigeo
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): ALCALA, JOSE H
• Application Number:
  US09/771,600
• Publication Number:
  US 20010010274A1
• Time in Patent Office: 546 Days
• Field of Search: 174/261, 174/255, 174/256, 174/257, 361/780, 361/777, 361/778, 361/779, 361/792, 361/793, 361/794, 361/795
• US Class Current: 174/262
• CPC Class Codes: G01R 31/2805 Bare printed circuit boards
• CPC Class Codes: G01R 31/2812 Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance of connections G01R31/66
• CPC Class Codes: G01R 31/2818 using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors G01R31/2805 takes precedence; printed circuits having, e.g. symbols, test patterns or visualisation means H05K1/0266
• CPC Class Codes: H01P 3/088 Stacked transmission lines
• CPC Class Codes: H05K 1/0253 Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings H05K1/0251 takes precedence
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 2201/0191 wherein the thickness of the dielectric plays an important role
• CPC Class Codes: H05K 2201/09672 Superposed layout, i.e. in different planes parallel traces in one plane H05K2201/09236
• CPC Class Codes: H05K 2201/0969 Apertured conductors

Abstract

A plain layer in a forming area of a measuring wiring pattern is patterned so that its copper-containing amount may be coincided with a copper-containing amount in a forming area of a measurement target signal wiring pattern. Thereby, it is possible to coincide a thickness of an insulating layer in the forming area of the measuring wiring pattern with a thickness of the insulating layer in the forming area of the measurement target signal wiring pattern, thus reducing a measuring error of the characteristic impedance based on a difference of a thickness of the insulating layer. Using the measuring wiring pattern, it is possible to measure a correct characteristic impedance of the measurement target signal wiring pattern.

Claims

1. A print board comprising:

a patterned conductive layer which is patterned on a first insulating layer;

a second insulating layer formed on said first insulting layer and patterned conductive layer; and

a wiring pattern layer formed on said second insulating layer, wherein

said wiring pattern layer comprises a measurement target signal wiring pattern for which characteristic impedance is to be measured and a measuring wiring pattern through which a measuring signal for measuring the characteristic impedance of said measurement target signal wiring pattern is flowed, and

said patterned conductive layer comprises a first pattern above which said measurement target signal wiring pattern is formed and a second pattern above which said measuring wiring pattern is formed, the density of a conductive material first pattern being approximately the same as the density of a conductive material of said second pattern.

2. The print board according to claim 1, wherein said first pattern includes a conductive material removal area from which a conductive material is removed.

3. The print board according to claim 2, wherein said conductive material removal area is a via hole for an interlayer hole or a through hole, or a cutout portion.

4. The print board according to claim 2, wherein said conductive material removal area is located more inside than said measuring wiring pattern.

5. The print board according to claim 1, wherein a diameter of a via hole for an interlayer hole or a through hole in the first pattern is smaller than a diameter in the second pattern.

6. The print board according to claim 2, wherein a diameter of a via hole for an interlayer hole or a through hole in the first pattern is smaller than a diameter of the via hole in the second pattern.

7. The print board according to claim 1, wherein a slit width for separating the conductive layer in the first pattern is smaller than a slit width in the second pattern.

8. The print board according to claim 2, wherein a slit width for separating the conductive layer in the first pattern is smaller than a slit width in the second pattern.

9. The print board according to claim 1, wherein said conductive layer comprises at least one of a power source pattern and ground pattern.