Active matrix display device having multiple gate electrode portions
First Claim
Patent Images
1. An active matrix type EL display device comprising:
- a pixel portion over a substrate;
a driving circuit over the same substrate;
at least a thin film transistor in the pixel portion, said thin film transistor including;
a semiconductor island including;
a source region, a drain region, and a plurality of channel forming regions each being formed between the source region and the drain region;
a gate insulating film; and
a gate electrode being adjacent to the semiconductor island and having the gate insulating film between the semiconductor island and the gate electrode, wherein the gate electrode is divided into a plurality of gate electrode portions, wherein one of the gate electrode portions being the closest to the drain region has the narrowest width among the plurality of gate electrode portions, wherein a current flows from the source region to the drain region through each of the plurality of channel forming regions in a channel length direction.
0 Assignments
0 Petitions
Accused Products
Abstract
In a thin-film transistor of multi-gate structure, the width of a channel forming region 108 closest to a drain region 102 is made the narrowest. This prevents a transistor structure closest to the drain region from first deteriorating. Further, the channel length at the vicinity of a center of an active layer is intentionally widened, so that the amount of current flowing through the vicinity of the center of the active layer is decreased and the deteriorating phenomenon due to heat accumulation is prevented. Therefore, a semiconductor device with a high reliability is realized.
57 Citations
14 Claims
-
1. An active matrix type EL display device comprising:
-
a pixel portion over a substrate;
a driving circuit over the same substrate;
at least a thin film transistor in the pixel portion, said thin film transistor including;
a semiconductor island including;
a source region, a drain region, and a plurality of channel forming regions each being formed between the source region and the drain region;
a gate insulating film; and
a gate electrode being adjacent to the semiconductor island and having the gate insulating film between the semiconductor island and the gate electrode, wherein the gate electrode is divided into a plurality of gate electrode portions, wherein one of the gate electrode portions being the closest to the drain region has the narrowest width among the plurality of gate electrode portions, wherein a current flows from the source region to the drain region through each of the plurality of channel forming regions in a channel length direction. - View Dependent Claims (2, 3)
wherein the EL display device is used in one selected from the group consisting of a TV camera, a head mount display, a car navigation system, a projector, a video camera, a personal computer. -
3. A device according to claim 1, wherein each of the source and drain regions comprises one selected from the group consisting of phosphorus and boron.
-
-
4. An active matrix type EL display device comprising:
-
a pixel portion over a substrate;
a driving circuit portion over the same substrate;
at least a thin film transistor in the pixel portion, said thin film transistor including;
a semiconductor island including;
a source region, a drain region, and at least a first channel forming region, a second channel forming region, and a third channel forming region, each being formed between the source region and the drain region;
a gate insulating film; and
a gate electrode, adjacent to the semiconductor island and having the gate insulating film between said semiconductor island and said gate electrode, wherein the gate electrode is divided into at least a first gate electrode portion, a second gate electrode portion and a third gate electrode portion, wherein the first gate electrode portion is formed over the first channel forming region and the closest to the drain region, the first channel forming region being the closest to the drain region, wherein the first gate electrode has the narrowest width so that the first channel forming region has the shortest channel length, wherein the third gate electrode portion is formed over the third channel forming region and the closest to the source region thereby the third channel forming region being defined the closest to the source region, wherein the third gate electrode portion has the widest width so that the third channel forming region has the longest channel length, wherein a current flows from the source region to the drain region through each of the first, second and third channel forming regions in a channel length direction. - View Dependent Claims (5, 6, 7, 8, 9)
wherein each of the first, second and third gate electrode portions has two end portions and a middle portion formed between the two end portions, each of the end and middle portions being located in a channel width direction; wherein the middle portion of each of the first, second and third gate electrodes has the widest width so that a middle portion of each of the first, second and third channel forming regions has the longest channel length.
-
-
9. A device according to claim 4, wherein each of the source and drain regions comprises one selected from the group consisting of phosphorus and boron.
-
10. An active matrix type EL display device comprising:
-
a pixel portion over a substrate;
a driving circuit portion over the same substrate;
at least a thin film transistor in the pixel portion, said thin film transistor including;
a semiconductor island including;
a source region;
a drain region;
at least a first channel forming region, a second channel forming region and a third channel forming region, each being formed between the source and drain regions;
a gate insulating film;
a gate electrode adjacent to the semiconductor island having the gate insulating film therebetween;
wherein the gate electrode is divided into at least a first gate electrode portion, a second gate electrode portion and a third gate electrode portion;
wherein the first gate electrode portion is formed over the first channel forming region and the closest to the drain region thereby the first channel forming region being defined the closest to the drain region;
wherein the first gate electrode portion has the narrowest width so that the first channel forming region has the shortest channel length;
wherein the third gate electrode portion is formed over the third channel forming region and the closest to the source region thereby the third channel forming region being defined the closest to the source region;
wherein the third gate electrode portion has the widest width so that the third channel forming region has the longest channel length;
wherein each of the first, second and third gate electrode portions has two end portions and a middle portion formed between the two end portions, each of the end and middle portions being located in a channel width direction;
wherein the middle portion of each of the first, second and third gate electrodes has the widest width so that a middle portion of each of the first, second and third channel forming regions has the longest channel length; and
wherein a current flows from the source region to the drain region through each of the first, second, and third channel forming regions in a channel length direction. - View Dependent Claims (11, 12, 13, 14)
-
Specification