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Architecture for field programmable gate array

  • US 6,426,649 B1
  • Filed: 12/29/2000
  • Issued: 07/30/2002
  • Est. Priority Date: 12/29/2000
  • Status: Expired due to Term
First Claim
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1. A field programmable gate array, comprising:

  • a programmable interconnect structure; and

    a plurality of logic modules, each of said logic modules comprising;

    a first combinatorial logic circuit having a plurality of input leads and an output lead, said input leads extending from said logic module and into said programmable interconnect structure;

    a second combinatorial logic circuit having a plurality of input leads and an output lead, said input leads extending from said logic module and into said programmable interconnect structure;

    a first multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, said first data input lead being connected to said output lead of said first combinatorial logic circuit within said logic module, said second data input lead being connected to said output lead of said second combinatorial logic circuit within said logic module, said output lead extending from said logic module and into said programmable interconnect structure;

    a second multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, said first data input lead of said second multiplexer being connected to said output lead of said second combinatorial logic circuit within said logic module;

    a first sequential logic element having a data input lead, a clock input lead, and a data output lead, said data input lead of said sequential logic element being coupled to said output lead of said first multiplexer, said data output lead extending from said logic module and into said programmable interconnect structure; and

    a second sequential logic element having a data input lead, a clock input lead, and a data output lead, said data input lead of said second sequential logic element being coupled to said output lead of said second multiplexer, said data output lead of said second sequential logic element extending from said logic module and into said programmable interconnect structure.

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