Architecture for field programmable gate array

• US 6,426,649 B1
• Filed: 12/29/2000
• Issued: 07/30/2002
• Est. Priority Date: 12/29/2000
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Eaton, David D., Fu, Robert, Chan, Andrew K., Yee, Kevin K.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/751,440
• Time in Patent Office: 578 Days
• Field of Search: 326/38-41, 326/83, 326/86, 326/56-58, 327/293, 327/292, 327/565
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor. The gate of the protection transistor is coupled to a primary charge pump that is shared with multiple drivers as well as a secondary charge pump associated with the driver.

Claims

1. A field programmable gate array, comprising:

a programmable interconnect structure; and

a plurality of logic modules, each of said logic modules comprising;

a first combinatorial logic circuit having a plurality of input leads and an output lead, said input leads extending from said logic module and into said programmable interconnect structure;

a second combinatorial logic circuit having a plurality of input leads and an output lead, said input leads extending from said logic module and into said programmable interconnect structure;

a first multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, said first data input lead being connected to said output lead of said first combinatorial logic circuit within said logic module, said second data input lead being connected to said output lead of said second combinatorial logic circuit within said logic module, said output lead extending from said logic module and into said programmable interconnect structure;

a second multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, said first data input lead of said second multiplexer being connected to said output lead of said second combinatorial logic circuit within said logic module;

a first sequential logic element having a data input lead, a clock input lead, and a data output lead, said data input lead of said sequential logic element being coupled to said output lead of said first multiplexer, said data output lead extending from said logic module and into said programmable interconnect structure; and

a second sequential logic element having a data input lead, a clock input lead, and a data output lead, said data input lead of said second sequential logic element being coupled to said output lead of said second multiplexer, said data output lead of said second sequential logic element extending from said logic module and into said programmable interconnect structure.

2. The field programmable gate array of claim 1, wherein said first combinatorial logic circuit has five input leads, four of said input leads extend from said logic module and into said into said programmable interconnect structure.

3. The field programmable gate array of claim 1, wherein said first combinatorial logic circuit comprises:

a first input AND gate having an output lead;

a second input AND gate having an output lead; and

a third multiplexer having a first data input lead coupled to said output lead of said first two input AND gate, a second data input lead coupled to said output lead of said second two input AND gate, a select input lead and an output lead, said output lead being coupled to said data input lead of said first multiplexer.

4. The field programmable gate array of claim 3, said logic modules further comprising a fourth multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, said output lead being connected to said select input lead of said third multiplexer.

5. The field programmable gate array of claim 4, said logic modules further comprising a first six input AND gate having an output lead connected to a first data input lead of said fourth multiplexer.

6. The field programmable gate array of claim 1, said logic modules further comprising a third combinatorial logic circuit having a plurality of input leads and an output lead, said input leads extending from said logic module and into said programmable interconnect structure, said output lead being coupled to said an input lead of said first combinatorial logic circuit and an input lead of said second combinatorial logic circuit and extending from said logic module and into said programmable interconnect structure.

7. The field programmable gate array of claim 6, said logic modules further comprising a fourth combinatorial logic circuit having a plurality of input leads and an output lead, said input leads extending from said logic module and into said programmable interconnect structure, said output lead being coupled to said select input lead of said first multiplexer and extending from said logic module and into said programmable interconnect structure.

8. The field programmable gate array of claim 7, wherein said third combinatorial logic circuit is a first six input AND gate and said fourth combinatorial logic circuit is a second six input AND gate.

9. The field programmable gate array of claim 8, wherein at least one input lead of said first six input AND gate and at least one input lead of said second six input AND gate are programmable coupled to a clock bus in said programmable interconnect structure.

10. The field programmable gate array of claim 1, wherein said second data input lead and said select input lead of said second multiplexer extend from said logic module and into said into said programmable interconnect structure.

11. A logic cell for a programmable application specific integrated circuit, said logic cell comprising:

a combinatorial logic circuit having a plurality of input leads and an output lead;

a first sequential logic element having a data input lead, a clock input lead, and a data output lead, said data input lead of said first sequential logic element being selectively coupled to said output lead of said combinatorial logic circuit, said data output lead of said first sequential logic element extending from said logic module and into said programmable interconnect structure; and

a second sequential logic element having a data input lead, a clock input lead, and a data output lead, said data input lead of said second sequential logic element being selectively coupled to said output lead of said combinatorial logic circuit, said data output lead of said second sequential logic element extending from said logic module and into said programmable interconnect structure.

12. The logic cell of claim 11, further comprising:

a first means for selectively coupling said output lead of said combinatorial logic circuit to said data input lead of said first sequential logic element; and

a second means for selectively coupling said output lead of said combinatorial logic circuit to said data input lead of said second sequential logic element.

13. The logic cell of claim 12, wherein said first means is a first multiplexer and said second means is a second multiplexer.

14. A programmable device, comprising:

a programmable interconnect structure; and

a plurality of logic modules, each of said logic modules having at least one output lead and a driver coupled between at least one output lead and said programmable interconnect structure, said driver comprising;

an inverter having an input lead and an output lead, said input lead of said inverter coupled to said output lead of said logic module,

a protection transistor having a first terminal, a second terminal and a gate terminal, said first terminal coupled to said output lead of said inverter, said second terminal coupled to said programmable interconnect structure;

a primary charge pump coupled to said gate; and

a secondary charge pump coupled to said primary charge pump and to said gate terminal of said protection transistor.

15. The programmable device of claim 14, wherein there are no transistors disposed between said protection transistor and said inverter, and there are no transistors disposed between said protection transistor and said programmable interconnect structure.

16. A programmable device comprising:

an array of logic cells;

a programmable interconnect structure coupled to said logic cells;

an I/O circuit comprising;

an I/O pad; and

an output register having an input terminal coupled to said programmable interconnect structure and an output terminal coupled to said I/O pad and said programmable interconnect structure,

wherein said I/O circuit further comprises;

a multiplexer having a first data terminal coupled to said output terminal of said output register and a second data terminal coupled directly to said input terminal of said output register, and an output terminal coupled to said I/O pad.

17. A programmable device comprising:

an array of logic cells;

a programmable interconnect structure coupled to said logic cells;

an I/O circuit comprising;

an I/O pad; and

an output register having an input terminal coupled to said programmable interconnect structure and an output terminal coupled to said I/O pad and said programmable interconnect structure,

wherein said I/O circuit further comprises;

a buffer having an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad, said buffer having an enable terminal; and

an output enable register having an input terminal coupled directly to said programmable interconnect structure and an output terminal coupled to said enable terminal of said buffer.

18. The programmable device of claim 17, wherein said I/O circuit further comprises:

a multiplexer having a first data terminal coupled to said output terminal of said output enable register, a second data terminal coupled to said input terminal of said output enable register, and an output terminal coupled to said input terminal of said buffer.

19. A programmable device comprising:

an array of logic cells;

a programmable interconnect structure coupled to said logic cells;

an I/O circuit comprising;

an I/O pad; and

an output register having an input terminal coupled to said programmable interconnect structure and an output terminal coupled to said I/O pad and said programmable interconnect structure,

wherein said I/O circuit further comprises a buffer with an adjustable slew rate, said buffer comprising an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad and a slew rate control terminal coupled to said programmable interconnect structure.

20. The programmable device of claim 19, wherein said buffer comprises:

at least one inverter having an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad, said inverter coupled to a voltage source and to ground potential through a resistive element;

a logic gate having an input terminal coupled to said slew rate control terminal, and an output terminal; and

a first transistor disposed between said at least one inverter and said ground potential in parallel with said resistive element, said first transistor having a gate coupled to said output terminal of said logic gate, said first transistor having less resistance than said resistive element.

21. The programmable device of claim 20, wherein said buffer further comprises:

a second inverter having an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad, said second inverter coupled to a voltage source through a second resistive element and to ground potential; and

a second transistor disposed between said second inverter and said voltage source in parallel with said second resistive element, said second transistor having a gate coupled to said output terminal of said logic gate, said second transistor having less resistance than said second resistive element.

22. The programmable device of claim 21, wherein said resistive element is a third transistor that is smaller than said first transistor and said second resistive element is a fourth transistor smaller than said second transistor, wherein said third transistor and said fourth transistor enable and disable said buffer.

23. A programmable device comprising:

an array of logic cells;

a programmable interconnect structure coupled to said logic cells;

an I/O circuit comprising;

an I/O pad;

an input register having an input terminal coupled to said I/O pad and an output terminal coupled to said programmable interconnect structure;

an output register having an input terminal coupled to said programmable interconnect structure and an output terminal coupled to said I/O pad; and

a buffer disposed between said output terminal of said output register and said I/O pad, said buffer having an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad, said buffer having an enable terminal; and

an output enable register having an input terminal coupled to said programmable interconnect structure and an output terminal coupled to said enable terminal of said buffer.

24. The programmable device of claim 23, wherein said output terminal of said output register is also coupled to said programmable interconnect structure.

25. The programmable device of claim 23, wherein said I/O circuit further comprises a buffer with an adjustable slew rate, said buffer comprising an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad and a slew rate control terminal coupled to said programmable interconnect structure.

26. The programmable device of claim 25, wherein said buffer comprises:

at least one inverter having an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad, said inverter coupled to a voltage source and to ground potential through a resistive element;

a logic gate having an input terminal coupled to said slew rate control terminal, and an output terminal; and

a first transistor disposed between said at least one inverter and said ground potential in parallel with said resistive element, said first transistor having a gate coupled to said output terminal of said logic gate, said first transistor having less resistance than said resistive element.

27. The programmable device of claim 26, wherein said buffer further comprises:

a second inverter having an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad, said second inverter coupled to a voltage source through a second resistive element and to ground potential; and

a second transistor disposed between said second inverter and said voltage source in parallel with said second resistive element, said second transistor having a gate coupled to said output terminal of said logic gate, said second transistor having less resistance than said second resistive element.

28. The programmable device of claim 27, wherein said resistive element is a third transistor that is smaller than said first transistor and said second resistive element is a fourth transistor smaller than said second transistor.

29. The programmable device of claim 23, said programmable device further comprising a boundary scan circuit, said boundary scan circuit using said input register, said output register and said output enable register of said I/O circuit.

30. The programmable device of claim 23, wherein said input register has an enable terminal, said output enable register has an enable terminal, said programmable device further comprising:

at least one I/O control pad programmably coupled to said enable terminal of said input register and programmably coupled to said enable terminal of said output enable register.

31. The programmable device of claim 30, wherein said input register has a reset terminal, said output enable register has a reset terminal and said output register has a reset terminal, said at least one I/O control pad being programmably coupled to said reset terminals of said input register, said output enable register and said output register.

32. The programmable device of claim 30, wherein said input register has a clock terminal, said output enable register has a clock terminal and said output register has a clock terminal, said at least one I/O control pad being programmably coupled to said clock terminals of said input register, said output enable register and said output register.

33. The programmable device of claim 30, further comprising:

a hardwired clock bus;

a multiplexer having a first data terminal programmably coupled to said at least one I/O control pad and a second data terminal programmably coupled to said hardwired clock bus, and an output terminal coupled to said clock terminals of said input register, said output register and said output enable register.

34. The programmable device of claim 30, said at least one I/O control pad being programmably coupled to said input terminal of said output enable register.

35. A programmable device comprising:

an array of logic cells;

a programmable interconnect structure coupled to said logic cells;

an I/O circuit comprising;

an I/O pad;

an output register having an input terminal coupled to said programmable interconnect structure and an output terminal; and

a buffer with an adjustable slew rate, said buffer comprising an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad and a slew rate control terminal coupled to said programmable interconnect structure.

36. The programmable device of claim 35, wherein said buffer comprises:

at least one inverter having an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad, said inverter coupled to a voltage source and to ground potential through a resistive element;

a logic gate having an input terminal coupled to said slew rate control terminal, and an output terminal; and

a first transistor disposed between said at least one inverter and said ground potential in parallel with said resistive element, said first transistor having a gate coupled to said output terminal of said logic gate, said first transistor having less resistance than said resistive element.

37. The programmable device of claim 36, wherein said buffer further comprises:

a second inverter having an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad, said second inverter coupled to a voltage source through a second resistive element and to ground potential; and

a second transistor disposed between said second inverter and said voltage source in parallel with said second resistive element, said second transistor having a gate coupled to said output terminal of said logic gate, said second transistor having less resistance than said second resistive element.

38. The programmable device of claim 37, wherein said resistive element is a third transistor that is smaller than said first transistor and said second resistive element is a fourth transistor smaller than said second transistor, wherein said third transistor and said fourth transistor enable and disable said buffer.

39. A programmable device comprising:

an array of logic cells;

a programmable interconnect structure coupled to said logic cells;

an I/O circuit comprising;

an I/O pad;

an input register having an input terminal and an output terminal coupled to said programmable interconnect structure;

a multiplexer having a first data terminal coupled to said I/O pad, a second data terminal, and an output terminal coupled to said input terminal of said input register; and

a differential translator having a first input terminal coupled to said I/O pad, a second input terminal coupled to a voltage reference source, and an output terminal coupled to said second data terminal of said multiplexer.

40. The programmable device of claim 39, wherein said second input terminal of said differential translator may be programmably coupled to at least two voltage reference sources.

41. The programmable device of claim 40, wherein said I/O circuit is programmably coupled to a plurality of voltage sources.

42. The programmable device of claim 40, wherein said multiplexer has a select terminal coupled to said programmable interconnect structure.

43. The programmable device of claim 39, wherein said output terminal of said multiplexer is also coupled to said programmable interconnect structure.

44. A field programmable gate array, comprising:

an array of logic cells divided into quadrants;

a clock pad; and

a clock network coupled to said clock pad, said clock network having clock buses extending into the approximate center of each quadrant and bisecting each quadrant of said array of logic cells.

45. The field programmable gate array of claim 44, wherein said clock network comprises:

a primary clock bus coupled to said clock pad and extending in a horizontal direction between said quadrants;

a plurality of second clock buses each of which is coupled to said primary clock bus and extends in a vertical direction to the approximate center of a quadrant;

a plurality of third clock buses each of which is located in a quadrant and is coupled to one of said plurality of second clock buses and extends in a horizontal direction bisecting said quadrant; and

a plurality of fourth clock buses coupled to each of said third clock buses, wherein a first portion of fourth clock buses vertically extend from said third clock buses in a first direction, and a second portion of fourth clock buses vertically extend from said third clock buses in a second direction opposite said first direction.

46. The field programmable gate array of claim 45, wherein each bus in said first portion of fourth clock buses may be programmably coupled to a first plurality of logic cells, and each bus in said second portion of fourth clock buses may be programmably coupled to a second plurality of logic cells.

47. The field programmable gate array of claim 46, wherein said first plurality of logic cells and said second plurality of logic cells has the same number of logic cells.

48. The field programmable gate array of claim 45, wherein each of said second clock buses is coupled to a third clock bus at the approximate center of said third clock bus.

49. The field programmable gate array of claim 45, further comprising a fifth clock bus extending from said clock pad to said primary clock bus, said fifth clock bus being coupled to the approximate center of said primary clock bus.

50. The field programmable gate array of claim 44, further comprising:

a phase locked loop circuit having an input terminal coupled to said primary clock bus, a feedback terminal coupled to one of said fourth clock buses, and an output terminal coupled a second primary clock bus that is parallel to said primary clock bus;

a second plurality of second clock buses each of which is coupled to said second primary clock bus and is parallel with one of said plurality of second clock buses; and

a plurality of multiplexers, each multiplexer having a first data terminal receiving one of said plurality of second clock buses, a second data terminal receiving one of said second plurality of second clock buses, and an output terminal coupled to one of said plurality of third clock buses.

51. The field programmable gate array of claim 50, wherein said phase locked loop circuit comprises:

a first programmable divide by n circuit having an input terminal coupled to said primary clock bus and an output terminal;

a phase detector having a first input terminal coupled to said output terminal of said first programmable divide by n circuit, a second input terminal and an output terminal;

a low pass filter having an input terminal coupled to said output terminal of said phase detector and an output terminal;

a voltage controlled oscillator having an input terminal coupled to said output terminal of said low pass filter and an output terminal;

a second programmable divide by n circuit having an input terminal coupled to said output terminal of said voltage controlled oscillator, and an output terminal coupled to said second primary clock bus that is parallel to said primary clock bus; and

a third programmable divide by n circuit having an feedback terminal coupled to said one of said fourth clock buses and an output terminal coupled to said second input terminal of said phase detector.

52. The field programmable gate array of claim 51, wherein said first programmable divide by n circuit comprises:

a multiplexer having a first data terminal, a second data terminal, a third data terminal, and an output terminal coupled to said first input terminal of said phase detector, said first data terminal being coupled to said primary clock bus;

a divide by 2 circuit, said second data terminal being coupled to said primary clock bus through said divide by 2 circuit; and

a divide by 4 circuit, said third data terminal being coupled to said primary clock bus through said divide by 4 circuit.

53. The field programmable gate array of claim 52, wherein said third programmable divide by n circuit comprises:

a second multiplexer having a first data terminal, a second data terminal, a third data terminal, and an output terminal coupled to said second input terminal of said phase detector, said first data terminal being coupled to said one of said fourth clock buses;

a second divide by 2 circuit, said second data terminal being coupled to said one of said fourth clock buses through said second divide by 2 circuit; and

a second divide by 4 circuit, said third data terminal being coupled to said one of said fourth clock buses through said divide by 4 circuit.

54. The field programmable gate array of claim 51, wherein said second programmable divide by n circuit comprises:

a multiplexer having a first data terminal, a second data terminal, and an output terminal coupled to said second primary clock bus that is parallel to said primary clock bus, said first data terminal being coupled to said output terminal of said voltage controlled oscillator; and

a divide by 2 circuit, said second data terminal being coupled to said voltage controlled oscillator through said divide by 2 circuit.

55. The field programmable gate array of claim 44, wherein said clock pad is a dedicated clock pad, and said clock network provides a dedicated clock signal to each quadrant.

56. A field programmable gate array, comprising:

an array of logic cells;

a clock network programmably coupled to said logic cells, said clock network providing a clock signal to selected logic cells;

a phase locked loop circuit coupled to said clock network, said phase locked loop circuit comprising;

a first programmable divide by n circuit receiving said clock signal having an input terminal coupled to said clock network, and having an output terminal;

a phase detector having a first input terminal coupled to said output terminal of said first programmable divide by n circuit, and having a second input terminal and an output terminal;

a low pass filter having an input terminal coupled to said output terminal of said phase detector and having an output terminal;

a voltage controlled oscillator having an input terminal coupled to said output terminal of said low pass filter and having an output terminal;

a second programmable divide by n circuit having an input terminal coupled to said output terminal of said voltage controlled oscillator, and having an output terminal coupled to said clock network; and

a third programmable divide by n circuit having an feedback terminal coupled to said clock network and having an output terminal coupled to said second input terminal of said phase detector.

57. The field programmable gate array of claim 56, wherein said first programmable divide by n circuit comprises:

a multiplexer having a first data terminal, a second data terminal, a third data terminal, and an output terminal coupled to said first input terminal of said phase detector, said first data terminal being coupled to said clock network;

a divide by 2 circuit, said second data terminal being coupled to said clock network through said divide by 2 circuit; and

a divide by 4 circuit, said third data terminal being coupled to said clock network through said divide by 4 circuit.

58. The field programmable gate array of claim 56, wherein said third programmable divide by n circuit comprises:

a second multiplexer having a first data terminal, a second data terminal, a third data terminal, and an output terminal coupled to said second input terminal of said phase detector, said first data terminal being coupled to said clock network;

a second divide by 2 circuit, said second data terminal being coupled to said clock network through said second divide by 2 circuit; and

a second divide by 4 circuit, said third data terminal being coupled to said clock network through said divide by 4 circuit.

59. The field programmable gate array of claim 56, wherein said second programmable divide by n circuit comprises:

a multiplexer having a first data terminal, a second data terminal, and an output terminal coupled to said second clock network, said first data terminal being coupled to said output terminal of said voltage controlled oscillator; and

a divide by 2 circuit, said second data terminal being coupled to said voltage controlled oscillator through said divide by 2 circuit.

60. A field programmable gate array comprising:

an array of logic cells;

routing resources having antifuses programming coupling said logic cells, wherein said array of logic cells and routing resources are divided into at least a first subsection and a second subsection;

a plurality of horizontal programming cells coupled to each subsection, wherein a first set of horizontal programming cells is coupled to said first subsection and a second set of horizontal programming cells is coupled to said second subsection;

a plurality of vertical programming cells, wherein a first set of vertical programming cells is coupled to said first subsection and a second set of vertical programming cells is coupled to said second subsection;

a plurality of power buses, a first set of power buses coupled to said first set of horizontal programming cells, a second set of power buses coupled to said second set of horizontal programming cells, a third set of power buses coupled to said first set of vertical programming cells, and a fourth set of power buses coupled to said second set of vertical programming cells.

61. The field programmable gate array of claim 60, wherein:

said first set of horizontal programming cells approximately bisects said first subsection and wherein a first subset of said first set of power buses is used to program antifuses in a first direction and a second subset of said first set of power buses is used to program antifuses in a second direction opposite said first direction; and

said first set of vertical programming cells approximately bisects said first subsection and wherein a first subset of said third set of power buses is used to program antifuses in a third direction orthogonal to said first direction and a second subset of said third set of power buses is used to program antifuses in a fourth direction opposite said third direction.

62. The field programmable gate array of claim 60, wherein there are a eight power buses and there are four power buses in said first set of power buses and four power buses in said second set of power buses, wherein said first set of power buses and said second set of power buses comprises at least one different power bus.

63. The field programmable gate array of claim 62, wherein there are four power buses in said third set of power buses and four power buses in said fourth set of power buses, wherein said third set of power buses and said fourth set of power buses comprises at least three different power buses.

64. The field programmable gate array of claim 63, wherein said first set of power buses and said third set of power buses comprises at least one different power bus, and said second set of power buses and said fourth set of power buses comprises at least one different power bus.

65. The field programmable gate array of claim 62, further comprising:

a third subsection and a fourth subsection of said array of logic cells and routing resources;

a third set of horizontal programming cells coupled to said third subsection and a fourth set of horizontal programming cells coupled to said fourth subsection;

a third set of vertical programming cells coupled to said third subsection and a fourth set of vertical programming cells coupled to said fourth subsection; and

a fifth set of power buses coupled to said third set of horizontal programming cells, a sixth set of power buses coupled to said fourth set of horizontal programming cells, a seventh set of power buses coupled to said third set of vertical programming cells, and an eighth set of power buses coupled to said fourth set of vertical programming cells.

66. The field programmable gate array of claim 65, wherein each set of horizontal programming cells and vertical programming cells approximately bisects a subsection of logic cells and routing resources.

67. A field programmable gate array comprising:

an array of logic cells divided into quadrants;

a set of horizontal programming cells coupled to and bisecting each quadrant;

a set of vertical programming cells coupled to and bisecting each quadrant, such that a pair of horizontal programming cells and vertical programming cells subdivides each quadrant into subquadrants; and

a plurality of power buses, wherein each set of horizontal programming cells and each set of vertical programming cells is coupled to a different set of power buses.

68. The field programmable gate array of claim 67, wherein there are eight power buses and each set of horizontal programming cells and each set of vertical programming cells is coupled to a different set of four power buses.

69. The field programmable gate array of claim 68, wherein each set of horizontal programming cells is coupled to a different set of power buses containing at least one different power bus.

70. The field programmable gate array of claim 68, wherein each set of vertical programming cells is coupled to a different set of power buses containing at least one different power bus.

71. The field programmable gate array of claim 68, wherein each set of horizontal programming cells provides a first subset of power buses in a first direction and a second subset of power buses in a second direction opposite said first direction.

72. The field programmable gate array of claim 71, wherein said first subset comprises two power buses and said second subset comprises a different two power buses.

73. The field programmable gate array of claim 71, wherein each set of vertical programming cells provides a third subset of power buses in a third direction orthogonal to said first direction and a fourth subset of power buses in a fourth direction opposite said third direction.

74. The field programmable gate array of claim 73, wherein said third subset comprises two power buses and said fourth subset comprises a different two power buses.

76. The programmable device of claim 70, further comprising:

a second NMOS transistor disposed between said low voltage programming source and said antifuse;

a second PMOS transistor disposed between said low voltage programming source and said antifuse, said second PMOS transistor being in parallel with said second NMOS transistor; and

said control circuit is coupled to said second NMOS transistor and said second PMOS transistor, said control circuit switching said second NMOS transistor and said second PMOS transistor on and off substantially simultaneously.

77. The programmable device of claim 70, wherein said control circuit provides a gate voltage at said first NMOS transistor that is approximately equal to the voltage provided by said high voltage programming source.

78. The programmable device of claim 70, further comprising a plurality of NMOS transistors disposed in series between said high voltage programming source and said antifuse and a plurality of PMOS transistors, each of which is in parallel with a corresponding NMOS transistor.

79. The programmable device of claim 70, further comprising a plurality of NMOS transistors disposed in series between said low voltage programming source and said antifuse and a plurality of PMOS transistors, each of which is in parallel with a corresponding NMOS transistor.

75. A programmable device comprising:

at least one antifuse;

a high voltage programming source switchably coupled to said antifuse;

a low voltage programming source switchably coupled to said antifuse;

a first NMOS transistor disposed between said high voltage programming source and said antifuse;

a first PMOS transistor disposed between said high voltage programming source and said antifuse, said first PMOS transistor being in parallel with said first NMOS transistor; and

a control circuit coupled to said first NMOS transistor and said first PMOS transistor, said control circuit switching said first NMOS transistor and said first PMOS transistor on and off substantially simultaneously.

80. A method of programming an antifuse in a programmable device, said method comprising:

switchably coupling said antifuse to a high voltage programming source through a first N channel transistor;

switchably coupling said antifuse to said high voltage programming source through a first P channel transistor in parallel with said first N channel transistor;

switchably coupling said antifuse to a low voltage programming source through a second N channel transistor; and

switchably coupling said antifuse to said low voltage programming source through a second P channel transistor in parallel with said first N channel transistor.

81. The method of claim 80, further comprising:

switchably coupling said antifuse to said high voltage programming source through a first plurality of serial N channel transistors;

switchably coupling said antifuse to said high voltage programming source through a first plurality of serial P channel transistor, each of said serial P channel transistors being in parallel with one of said first plurality of serial N channel transistors;

switchably coupling said antifuse to said low voltage programming source through a second plurality of serial N channel transistors; and

switchably coupling said antifuse to said low voltage programming source through a second plurality of serial P channel transistor, each of said second plurality of serial P channel transistors being in parallel with one of said second plurality of serial N channel transistors.

82. The method of claim 80, further comprising:

switchably coupling said antifuse to said low voltage programming source through a third N channel transistor that is in series with said second plurality of serial N channel transistors.

83. The method of claim 82, wherein there are three N channel transistors in said first plurality of serial N channel transistors, three P channel transistors in said first plurality of serial P channel transistors, two N channel transistors in said second plurality of serial N channel transistors, and two P channel transistors in said second plurality of serial P channel transistors.

84. A programmable device comprising:

an array of logic cells;

a programmable interconnect structure coupled to said logic cells;

an I/O circuit;

at least one I/O control pad; and

a multiplexer having a first data terminal coupled to said at least one I/O control pad, a second data terminal coupled to said programmable interconnect structure, and an output terminal coupled to said I/O circuit and said programmable interconnect structure.

85. The programmable device of claim 84, wherein said I/O circuit comprises:

an I/O pad;

an input register having an input terminal coupled to said I/O pad, an enable terminal coupled to said I/O control pad, and an output terminal coupled to said programmable interconnect structure;

an output register having an input terminal coupled to said programmable interconnect structure and an output terminal coupled to said I/O pad; and

a buffer disposed between said output terminal of said output register and said I/O pad, said buffer having an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad, said buffer having an enable terminal; and

an output enable register having an input terminal coupled to said programmable interconnect structure, an enable terminal coupled to said I/O control pad, and an output terminal coupled to said enable terminal of said buffer.