High speed, low-power inter-chip transmission system
First Claim
Patent Images
1. A data link on an integrated circuit comprising:
- a clock;
a push-pull driver circuit, clocked from the clock, driving a pair of differential data lines, one line driven high while the other line is pulled low; and
a receiver including a sense amplifier clocked from the clock.
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Accused Products
Abstract
In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the power requirements of the circuit. A clocked repeater within the link may itself comprise a clocked receiver and an H-bridge driver with line-to-line precharge.
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Citations
60 Claims
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1. A data link on an integrated circuit comprising:
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a clock;
a push-pull driver circuit, clocked from the clock, driving a pair of differential data lines, one line driven high while the other line is pulled low; and
a receiver including a sense amplifier clocked from the clock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An on-chip transmission system comprising:
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a clock;
a push-pull driver circuit, clocked from the clock, driving a signal on a pair of differential data lines, one line driven high while the other line is pulled low;
a regenerative repeater clocked from the clock to regenerate the signal from the driver circuit; and
a receiver including a sense amplifier which senses the signal regenerated by the repeater. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A regenerative repeater circuit comprising:
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a clocked sense amplifier clocked from a clock; and
a driver circuit clocked from the clock enabled by the sense amplifier, the driver circuit being a push-pull driver circuit driving a pair of differential lines, one line driven high while the other line is pulled low. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. A digital driver circuit comprising:
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a push-pull driver driving a pair of differential data output lines, one line driven high while the other line is pulled low; and
a data-line-to-data-line precharge circuit that shares charge between the data lines to a midpoint of voltage swing on the data lines. - View Dependent Claims (30, 31, 32, 33, 34)
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35. A digital driver circuit comprising:
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a push-pull driver driving a pair of differential output lines, one line driven high while the other line is pulled low; and
a timing circuit which controls timing of the push-pull driver, the timer circuit including a delay, the timing of which varies in a manner similar to timing variations in the driver circuit.
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36. A method of transmitting data in an integrated circuit comprising:
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at a push-pull driver circuit clocked from a clock, driving a pair of differential data lines, one line driven high while the other line is pulled low; and
at a receiver, sensing the signal on the differential data lines with a sense amplifier clocked from the clock. - View Dependent Claims (37, 38, 39, 40, 41)
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42. A method of transmitting data in a chip comprising:
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at a push-pull driver circuit clocked from a clock, driving a signal on a pair of differential lines, one line driven high while the other line is pulled low;
regenerating the signal from the driver circuit in a repeater clocked from the clock; and
sensing the signal from the repeater in a receiver. - View Dependent Claims (43, 44, 45, 46)
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47. A method of repeating a data signal comprising:
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sensing the data signal in a clocked sense amplifier clocked from a clock; and
from the output of the sense amplifier enabling a driver circuit clocked from a clock which repeats the signal received at the sense amplifier, the driver circuit being a push-pull driver circuit driving a pair of differential lines, one line driven high while the other line is pulled low. - View Dependent Claims (48, 49, 50)
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51. A method of driving a digital signal comprising:
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precharging a pair of differential output lines by sharing charge between the two lines to a midpoint of voltage swing on the output lines; and
driving the differential output lines, one line driven high while the other line is pulled low. - View Dependent Claims (52, 53)
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54. A method of driving a digital signal comprising:
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driving a pair of differential output lines through a push-pull driver, one line driven high while the other line is pulled low; and
from a clock signal, timing the push-pull driver circuit with a delay, the timing of which varies in a manner similar to timing variation in the driver circuit.
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55. A data link on an integrated circuit comprising:
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a clock;
driver means, clocked from the clock, for driving a pair of differential lines, one line driven high while the other line is pulled low; and
receiver means including a sense amplifier clocked from the clock.
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56. An on-chip transmission system comprising:
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a clock;
driver means, clocked from the clock, for driving a signal on a pair of differential lines, one line driven high while the other line is pulled low;
regenerative repeater means clocked from the clock for regenerating the signal from the driver circuit; and
receiver means for sensing the regenerated signal.
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57. A regenerative repeater circuit comprising:
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clocked sense amplifier means clocked from a clock for sensing a received signal; and
driver means clocked from the clock enabled by the sense amplifier means for driving the sensed signal on an output line.
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58. A digital driver circuit comprising:
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driver means for driving a pair of differential output lines, one line driven high while the other line is pulled low; and
precharge means for precharging the differential output lines by sharing charge between the lines to a midpoint of voltage swing on the differential output lines.
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59. A digital driver circuit comprising:
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push-pull driver means for driving a pair of differential output lines, one line driven high while the other line is pulled low; and
timing circuit means for controlling timing of the push-pull driver, the timing circuit means including a delay, the timing of which varies in a manner similar to timing variations in the driver circuit.
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60. A data link in an integrated circuit comprising:
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a clock;
a push-pull driver circuit driving a pair of differential lines through a low swing, one line driven high while the other line is pulled low;
a line-to-line precharge circuit which precharges the differential lines to a common voltage;
by sharing charge between the differential lines to a midpoint of voltage swing on the differential lines;
a timing circuit which clocks the push-pull driver circuit from the clock, the timing circuit including a delay, the timing of which varies in a manner similar to timing variations in the driver circuit;
a regenerative repeater clocked from the clock to regenerate the signal from the driver circuit; and
a receiver including a sense amplifier, clocked from the clock, to sense the regenerated signal from the repeater.
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Specification