High speed, low-power inter-chip transmission system

• US 6,426,656 B1
• Filed: 07/26/2000
• Issued: 07/30/2002
• Est. Priority Date: 04/19/2000
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Velio Communications, Inc. (Broadcom, Inc.)
• Inventors: Dally, William J., Hartman, Daniel K.
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US09/625,650
• Time in Patent Office: 734 Days
• Field of Search: 327/112, 327/309, 327/321, 327/51, 327/52, 327/56, 327/57, 327/89, 327/560-566, 365/203-208
• US Class Current: 327/51
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the power requirements of the circuit. A clocked repeater within the link may itself comprise a clocked receiver and an H-bridge driver with line-to-line precharge.

Claims

1. A data link on an integrated circuit comprising:

a clock;

a push-pull driver circuit, clocked from the clock, driving a pair of differential data lines, one line driven high while the other line is pulled low; and

a receiver including a sense amplifier clocked from the clock.

2. A data link as claimed in claim 1 wherein each of the differential lines is driven through a low swing.

3. A data link as claimed in claim 2 wherein the driver circuit comprises a data-line-to-data-line precharge circuit that shares charge between the data lines to a midpoint of voltage swing on the data lines.

4. A data link as claimed in claim 2 wherein the push-pull driver circuit is clocked through a timing circuit including a delay, the timing of which varies in a manner similar to timing variations in the driver circuit.

5. A data link as claimed in claim 1 wherein the driver circuit comprises a data-line-to-data-line precharge circuit that shares charge between the data lines to a midpoint of voltage swing on the data lines.

6. A data link as claimed in claim 1 wherein the driver circuit is an H-bridge, one line being driven high by a leg of the H as the other line is pulled low by a diagonal leg of the bridge.

7. A data link as claimed in claim 6 wherein the H-bridge comprises an NMOS transistor in each leg of the bridge.

8. A data link as claimed in claim 1 wherein the sense amplifier is isolated from the data lines by pass gates.

9. A data link as claimed in claim 1 wherein the data lines are connected only to gate terminals of input transistors of the sense amplifier.

10. A data link as claimed in claim 1 further comprising a regenerative repeater between the driver and sense amplifier, the repeater being clocked from the clock.

11. A data link as claimed in claim 1 wherein the drive circuit and receiver are formed of MOSFETs.

12. An on-chip transmission system comprising:

a clock;

a push-pull driver circuit, clocked from the clock, driving a signal on a pair of differential data lines, one line driven high while the other line is pulled low;

a regenerative repeater clocked from the clock to regenerate the signal from the driver circuit; and

a receiver including a sense amplifier which senses the signal regenerated by the repeater.

13. A transmission system as claimed in claim 12 wherein the driver circuit comprises a data-line-to-data-line precharge circuit that shares charge between the data lines to a midpoint of voltage swing on the data lines.

14. A transmission system as claimed in claim 12 wherein the driver circuit is an H-bridge, one line being driven high by a leg of the H as the other line is pulled low by a diagonal leg of the bridge.

15. A transmission system as claimed in claim 12 wherein the clock provides a plurality of clock signals having different phases.

16. A transmission system as claimed in claim 12 wherein the repeater comprises a sense amplifier, the output of which enables a driver circuit of the repeater.

17. A transmission system as claimed in claim 12 wherein the sense amplifier is isolated from the data lines by pass gates.

18. A transmission system as claimed in claim 12 wherein the data lines are connected only to gate terminals of input transistors of the sense amplifier.

19. A transmission system as claimed in claim 12 wherein the driver circuit and receiver are formed of MOSFETs.

20. A transmission system as claimed in claim 12 wherein each of the differential lines is driven through a low swing.

21. A transmission system as claimed in claim 20 wherein the push-pull driver circuit is clocked through a timing circuit including a delay, the timing of which varies in a manner similar to timing variations in the driver circuit.

22. A regenerative repeater circuit comprising:

a clocked sense amplifier clocked from a clock; and

a driver circuit clocked from the clock enabled by the sense amplifier, the driver circuit being a push-pull driver circuit driving a pair of differential lines, one line driven high while the other line is pulled low.

23. The repeater circuit as claimed in claim 22 wherein the driver circuit comprises a data-line-to-data-line precharge circuit that shares charge between the data lines to a midpoint of voltage swing on the data lines.

24. A repeater circuit as claimed in claim 22 wherein the driver circuit is an H-bridge, one line being driven high by a leg of the H as the other line is pulled low by a diagonal leg of the bridge.

25. A repeater circuit as claimed in claim 22 wherein the sense amplifier is gate isolated.

26. A repeater circuit as claimed in claim 22 formed of MOSFETs.

27. A repeater circuit as claimed in claim 22 wherein each line is driven through a low swing.

28. A repeater circuit as claimed in claim 27 wherein the push-pull driver circuit is clocked through a timing circuit including a delay, the timing of which varies in a manner similar to timing variations in the driver circuit.

29. A digital driver circuit comprising:

a push-pull driver driving a pair of differential data output lines, one line driven high while the other line is pulled low; and

a data-line-to-data-line precharge circuit that shares charge between the data lines to a midpoint of voltage swing on the data lines.

30. A digital driver circuit as claimed in claim 29 wherein the driver circuit is an H-bridge, one line being driven high by a leg of the H as the other line is pulled low by a diagonal leg of the bridge.

31. A digital driver circuit as claimed in claim 30 wherein the H-bridge comprises an NMOS transistor in each leg of the bridge.

32. A digital driver circuit as claimed in claim 29 formed of MOSFETs.

33. A digital driver circuit as claimed in claim 29 wherein each line is driven through a low swing.

34. A driver circuit as claimed in claim 33 wherein the push-pull driver circuit is clocked through a timing circuit including a delay, the timing of which varies in a manner similar to timing variations in the driver circuit.

35. A digital driver circuit comprising:

a push-pull driver driving a pair of differential output lines, one line driven high while the other line is pulled low; and

a timing circuit which controls timing of the push-pull driver, the timer circuit including a delay, the timing of which varies in a manner similar to timing variations in the driver circuit.

36. A method of transmitting data in an integrated circuit comprising:

at a push-pull driver circuit clocked from a clock, driving a pair of differential data lines, one line driven high while the other line is pulled low; and

at a receiver, sensing the signal on the differential data lines with a sense amplifier clocked from the clock.

37. A method as claimed in claim 36 wherein each of the differential lines is driven through a low swing.

38. A method as claimed in claim 37 further comprising precharging the differential lines through a data-line-to-data-line precharge circuit in the driver circuit that shares charge between the data lines to a midpoint of voltage swing on the data lines.

39. A method as claimed in claim 37 further comprising timing the push-pull driver circuit with a delay, the timing of which varies in a manner similar to timing variations in the driver circuit.

40. A method as claimed in claim 36 further comprising precharging the differential lines through a data-line-to-data-line precharge circuit in the driver circuit that shares charge between the data lines to a midpoint of voltage swing on the data lines.

41. A method as claimed in claim 36 further comprising regenerating the signal from the push-pull driver circuit in a repeater between the driver and the receiver, the repeater being clocked from the clock.

42. A method of transmitting data in a chip comprising:

at a push-pull driver circuit clocked from a clock, driving a signal on a pair of differential lines, one line driven high while the other line is pulled low;

regenerating the signal from the driver circuit in a repeater clocked from the clock; and

sensing the signal from the repeater in a receiver.

43. A method as claimed in claim 42 further comprising precharging the differential lines through a data-line-to-data-line precharge circuit in the driver circuit that shares charge between the data lines to a midpoint of voltage swing on the data lines.

44. A method as claimed in claim 42 wherein the clock is a multiphase clock.

45. A method as claimed in claim 42 wherein each of the differential lines is driven through a low swing.

46. A method as claimed in claim 45 further comprising timing the push-pull driver circuit with a delay, the timing of which varies in a manner similar to timing variations in the driver circuit.

47. A method of repeating a data signal comprising:

sensing the data signal in a clocked sense amplifier clocked from a clock; and

from the output of the sense amplifier enabling a driver circuit clocked from a clock which repeats the signal received at the sense amplifier, the driver circuit being a push-pull driver circuit driving a pair of differential lines, one line driven high while the other line is pulled low.

48. A method as claimed in claim 47 further comprising precharging the differential lines through a data-line-to-data-line precharge circuit in the driver circuit that shares charge between the data lines to a midpoint of voltage swing on the data lines.

49. A method as claimed in claim 47 wherein each of the differential lines is driven through a low swing.

50. A method as claimed in claim 49 further comprising timing the push-pull driver circuit with a delay wherein the push-pull driver circuit is clocked through a timing circuit including a delay the timing of which varies in a manner similar to timing variations in the driver circuit.

51. A method of driving a digital signal comprising:

precharging a pair of differential output lines by sharing charge between the two lines to a midpoint of voltage swing on the output lines; and

driving the differential output lines, one line driven high while the other line is pulled low.

52. A method as claimed in claim 51 wherein each of the differential lines is driven through a low swing.

53. A method as claimed in claim 52 further comprising timing the push-pull driver circuit with a delay, the timing of which varies in a manner similar to timing variations in the driver circuit.

54. A method of driving a digital signal comprising:

driving a pair of differential output lines through a push-pull driver, one line driven high while the other line is pulled low; and

from a clock signal, timing the push-pull driver circuit with a delay, the timing of which varies in a manner similar to timing variation in the driver circuit.

55. A data link on an integrated circuit comprising:

a clock;

driver means, clocked from the clock, for driving a pair of differential lines, one line driven high while the other line is pulled low; and

receiver means including a sense amplifier clocked from the clock.

56. An on-chip transmission system comprising:

a clock;

driver means, clocked from the clock, for driving a signal on a pair of differential lines, one line driven high while the other line is pulled low;

regenerative repeater means clocked from the clock for regenerating the signal from the driver circuit; and

receiver means for sensing the regenerated signal.

57. A regenerative repeater circuit comprising:

clocked sense amplifier means clocked from a clock for sensing a received signal; and

driver means clocked from the clock enabled by the sense amplifier means for driving the sensed signal on an output line.

58. A digital driver circuit comprising:

driver means for driving a pair of differential output lines, one line driven high while the other line is pulled low; and

precharge means for precharging the differential output lines by sharing charge between the lines to a midpoint of voltage swing on the differential output lines.

59. A digital driver circuit comprising:

push-pull driver means for driving a pair of differential output lines, one line driven high while the other line is pulled low; and

timing circuit means for controlling timing of the push-pull driver, the timing circuit means including a delay, the timing of which varies in a manner similar to timing variations in the driver circuit.

60. A data link in an integrated circuit comprising:

a clock;

a push-pull driver circuit driving a pair of differential lines through a low swing, one line driven high while the other line is pulled low;

a line-to-line precharge circuit which precharges the differential lines to a common voltage;

by sharing charge between the differential lines to a midpoint of voltage swing on the differential lines;

a timing circuit which clocks the push-pull driver circuit from the clock, the timing circuit including a delay, the timing of which varies in a manner similar to timing variations in the driver circuit;

a regenerative repeater clocked from the clock to regenerate the signal from the driver circuit; and

a receiver including a sense amplifier, clocked from the clock, to sense the regenerated signal from the repeater.