Shift register

• US 6,426,743 B1
• Filed: 02/09/2000
• Issued: 07/30/2002
• Est. Priority Date: 02/09/1999
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Kim, Jin Sang, Yoon, Sang Young, Yeo, Ju Cheon
• Primary Examiner(s): Chang, Kent
• Assistant Examiner(s): Sheng, Tom V.
• Application Number:
  US09/500,914
• Time in Patent Office: 902 Days
• Field of Search: 345/94, 345/98, 345/99, 345/100, 345/87, 345/213, 345/211, 345/204
• US Class Current: 345/213
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

In a shift register for driving a pixel row in a liquid crystal display device a plurality of stages are connected: to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator; to row lines; and in cascade, with respect to a scanning signal, for charging and discharging the row lines. Each stage of the shift register has a pull-up transistor, a pull-down transistor, and first to fourth transistors. The pull-up transistor has a control electrode and a conduction path connected between the first clock signal line and the output terminal. The pull-down transistor has a control electrode and a conduction path connected between the low level voltage line and the output terminal. The first and second transistors have conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor, and each has a control electrode connected commonly to the second clock signal line. The first and second transistors allow a voltage to be charged on the control electrode of the pull-up transistor. The third and fourth transistors have conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor, and each has a control electrode connected commonly to the third clock signal line. The third and fourth transistors allow a voltage to be charged on the control electrode of the pull-down transistor.

Claims

1. A shift register circuit comprising a plurality of cascaded stages connected to a start pulse input line and driving sequentially a plurality of row lines, each of the stages having an input terminal, an output terminal, a low level voltage line and being connected to first to third clock signal lines, the input terminal receiving an output signal of a previous stage, and the output terminal being connected to a row line, each one of the stages comprising:

a pull-up transistor having a control electrode and a conduction path connected between the first clock signal line and the output terminal;

a pull-down transistor having a control electrode and a conduction path connected between the low level voltage line and the output terminal;

first and second transistors having conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor, and each having a control electrode, connected commonly to the second clock signal line, the first and second transistors allowing a voltage to be charged on the control electrode of the pull-up transistor; and

third and fourth transistors having conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor and, each having a control electrode connected commonly to the third clock signal line, the third and fourth transistors allowing a voltage to be charged on the control electrode of the pull-down transistor.

2. The shift register of claim 1, wherein each one of the stages further includes:

fifth and sixth transistors having conduction paths connected in series between the control electrode of the pull-up transistor and the low level voltage line, and each having a control electrode connected commonly to the control electrode of the pull-down transistor, the fifth and sixth transistors allowing a voltage charged on the control electrode of the pull-up transistor to be discharged; and

seventh and eighth transistors having conduction paths connected in series between the control electrode of the pull-down transistor and the input terminal, and each having a control electrode connected commonly to the input terminal, the seventh and eighth transistors allowing a voltage charged on the control electrode of the pull-up transistor to be discharged.

3. The shift register of claim 1, wherein the start pulse on the input terminal and a second clock signal on the second clock signal line are simultaneously enabled during a first period such that a high logic level is charged on the control electrode of the pull-up transistor in response to the start pulse on the input terminal and the second clock signal.

4. The shift register of claim 3, wherein a first clock signal on the first clock signal line is subsequently enabled during a second period such that the pull-up transistor connects the output terminal to a high logic level.

5. The shift register of claim 3, wherein the first clock signal on the first clock signal line is subsequently disabled during a third period such that the pull-up transistor connects the output terminal to a low logic level.

6. A shift register including a plurality of cascaded stages connected to a start pulse input line and driving sequentially a plurality of row lines, each of the stages having an input terminal, an output terminal, a low level voltage line and being connected to first to third clock signal lines, the input terminal receiving an output signal of a previous stage, the output terminal being connected to a row line, each one of the stages comprising:

a pull-up transistor having a control electrode and a conduction path connected between the first clock signal line and the output terminal;

a pull-down transistor having a control electrode and a conduction path connected between the low level voltage line and the output terminal;

first and second transistors having conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor, and each having a control electrode, connected respectively to the input terminal and to the second clock signal line, the first and second transistors allowing a voltage to be charged on the control electrode of the pull-up transistor; and

third and fourth transistors having conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor, and each having a control electrode, connected commonly to the third clock signal line, the third and fourth transistors allowing a voltage to be charged on the control electrode of the pull-down transistor.

7. The shift register of claim 6, wherein each one of the stages further includes:

fifth and sixth transistors having conduction paths connected in series between the control electrode of the pull-up transistor and the low level voltage line, and each having a control electrode connected commonly to the control electrode of the pull-down transistor, the fifth and sixth transistors allowing a voltage charged on the control electrode of the pull-up transistor to be discharged; and

seventh and eighth transistors having conduction paths connected in series between the control electrode of the pull-down transistor and the input terminal, and each having a control electrode connected commonly to the input terminal, the seventh and eighth transistors allowing a voltage charged on the control electrode of the pull-up transistor to be discharged.

8. The shift register of claim 6, wherein the start pulse on the input terminal and a second clock signal on the second clock signal line are simultaneously enabled during a first period such that a high logic level is charged on the control electrode of the pull-up transistor in response to the start pulse on the input terminal and the second clock signal.

9. The shift register of claim 8, wherein a first clock signal on the first clock signal line is subsequently enabled during a second period such that the pull-up transistor connects the output terminal to a high logic level.

10. The shift register of claim 9, wherein the first clock signal on the first clock signal line is subsequently disabled during a third period such that the pull-up transistor connects the output terminal to a low logic level.

11. In a shift register stage having a low level voltage line, an input terminal, and an output terminal, and being connected to first to third clock signal lines, a pull-up transistor being disposed between the output terminal and the first clock signal line, and a pull-down transistor being disposed between the output terminal and the low level voltage line, a method of delaying a start pulse receiving at the input terminal by a clock period to produce an output pulse at the output terminal, said method comprising:

providing during a first clock period a start pulse on the input terminal and a clock pulse of a second clock signal on the second clock signal line to turn on the pull-up transistor and connect the output terminal with the first clock signal line having a low logic level;

providing during a second clock period a clock pulse of a first clock signal on the first clock signal line such that the pull-up transistor connects the output terminal to a high logic level;

disabling the clock pulse of the first clock signal on the first clock signal line during a third clock period such that the pull-up transistor connects the output terminal to a low logic level.

12. The method of claim 11, further comprising:

providing during a fourth clock period a clock pulse of a third clock signal on the third clock signal line such that the pull-down transistor connects the output terminal to the low level voltage line.

13. The method of claim 11, further comprising:

disabling during the second clock period the start pulse on the input terminal and the clock pulse of the second clock signal on the second clock signal line.