Cache memory for high latency and out-of-order return of texture data

• US 6,426,753 B1
• Filed: 07/01/1999
• Issued: 07/30/2002
• Est. Priority Date: 07/01/1999
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Migdal, Christopher
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/345,366
• Time in Patent Office: 1,125 Days
• Field of Search: 345/506, 345/501, 345/502, 345/505, 345/530, 345/545, 345/552, 345/557, 345/582
• US Class Current: 345/506
• CPC Class Codes: G06F 12/0859 with reload from main memory
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/455 Image or video data
• CPC Class Codes: G06T 15/04 Texture mapping

Abstract

A cache memory for high latency and out-of-order return of texture data. The present invention includes a texture cache memory that prefetches texture data before it is needed. Further, the texture cache memory counts the number of times a cache line is requested and a number of times the cache line is read, and determines whether the cache line is free by keeping track of the different between the two numbers. The texture cache memory of the present invention is capable of working efficiently in computer systems where there is a long latency from the time the texture data is requested and the time the texture data is available for use. In addition, the present invention is capable of handling texture data which enters into the texture cache memory in a different order from which it was requested. The present invention significantly improves performance of the texture data retrieval subsystem within network based or memory hierarchy based computer systems.

Claims

1. A computer system with a distributed texture memory architecture comprising:

a host processor for issuing commands;

a transmission network within said computer system that transmits packetized data over a plurality of paths;

a geometry subsystem coupled to said transmission network that performs geometry calculations corresponding to three-dimensional graphics according to commands from said host processor;

a rasterization subsystem coupled said transmission network that renders pixels based on geometry data generated by said geometry subsystem;

a plurality of memory chips coupled to said rasterization unit that store distributed texture data of a single texture map;

a texture cache subsystem coupled to said rasterization subsystem that caches said distributed texture data; and

a display subsystem coupled to said network for displaying textured three dimensional graphics onto a display.

2. A computer system as recited in claim 1 wherein said rasterization subsystem minimizes latency in said transmission network by prefetching said distributed texture data and storing said distributed texture data within said texture cache subsystem.

3. A computer system as recited in claim 2 wherein said texture cache subsystem comprises a cache address queue that stores prefetched cache addresses according to a first ordering.

4. A computer system as recited in claim 3 wherein said cache address queue comprises a FIFO memory.

5. A computer system as recited in claim 3 wherein said rasterization subsystem performs texture filtering using prefetched texture data according to said first ordering.

6. A computer system as recited in claim 5 wherein said rasterization subsystem performs texture filtering independent of an order in which said distributed texture data enter said texture cache subsystem.

7. A computer system as recited in claim 6 wherein said texture cache subsystem comprises a count memory for keeping track of said difference.

8. A computer system as recited in claim 2 wherein said texture cache subsystem comprises a cache memory having a plurality of cache lines and wherein said cache memory subsystem determines whether a respective one of said cache lines is free by keeping track of a difference between a number of times said respective cache line is requested and a number of times said respective cache line is read.

9. A computer system as recited in claim 7 wherein said respective cache line is available to receive new texture data when said difference is zero and wherein said respective cache line is unavailable to receive new texture data when said difference is larger than zero.

10. A graphics subsystem for a computer system having a distributed text memory architecture, said graphics subsystem comprising:

a) a texture request generator that generates texture requests and maps said texture requests to a plurality of cache addresses, wherein said texture requests are sent to distributed texture memories of said computer system according to a first ordering;

b) an address queue for receiving and storing said plurality of cache addresses according to said first ordering;

c) a cache memory for receiving texture responses from said distributed texture memories, wherein said texture responses enter said cache memory according to a second ordering; and

d) a texture filter for performing texture filtering by retrieving said texture responses from said cache memory in an order corresponding to said first ordering and independent of said second ordering.

11. A graphics subsystem as recited in claim 10 wherein said texture responses are prefetched and stored in said cache memory before texture filtering to minimize transmission latency.

12. A graphics subsystem as recited in claim 10 wherein said address queue provides said plurality of cache addresses to said texture filter according to said first ordering.

13. A graphics subsystem as recited in claim 12 wherein said address queue comprises a FIFO memory.

14. A graphics subsystem as recited in claim 10 further comprising a count memory for keeping track of a difference between a number of times a cache line of said cache memory is requested and a number of times said cache line is read.

15. A graphics subsystem as recited in claim 14 wherein said cache line is free to receive new texture response when said difference is zero and wherein said cache line is unavailable to receive new texture response when said difference is larger than zero.

16. In a computer system, a method of rendering pixels with texture data stored in distributed texture memories, said method comprising the steps of:

a) receiving a plurality texture memory addresses, said plurality of texture memory addresses corresponding to a plurality of cache address of a texture cache memory;

b) sending a plurality of texture requests to said distributed texture memories according to a first ordering;

c) receiving texture responses from said distributed texture memories and storing said texture responses within said texture cache memory, wherein said texture responses enter said texture cache memory according to a second ordering; and

d) retrieving said texture responses from said texture cache memory according to said first ordering and independent of said second ordering.

17. A method as recited in claim 16 wherein said step (b) and said step (d) are temporally separated to minimize data transmission latency.

18. A method as recited in claim 16 further comprising the steps of storing a plurality of cache addresses corresponding to said plurality of texture requests in an address queue according to said first ordering.

19. A method as recited in claim 18 wherein said address queue comprises a FIFO (first in first out) memory.

20. A method as recited in claim 16 further comprising a step of keeping track of a difference between a number of times a cache line of said texture cache memory is requested and a number of times said cache line is read.

21. A graphics subsystem as recited in claim 20 wherein said cache line is free to receive new texture data when said difference is zero and wherein said cache line is unavailable to receive new texture data when said difference is larger than zero.