Flash memory cell with contactless bit line, and process of fabrication

• US 6,426,896 B1
• Filed: 05/22/2000
• Issued: 07/30/2002
• Est. Priority Date: 05/22/2000
• Status: Expired due to Term

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Actrans Systems Inc. (Microchip Technology Incorporated)
• Inventors: Chen, Chiou-Feng
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Yoha, Connie C.
• Application Number:
  US09/576,394
• Time in Patent Office: 799 Days
• Field of Search: 365/185.26, 365/185.01, 365/185.28
• US Class Current: 365/185.26
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.

Claims

1. In a memory cell array:

a substrate, a plurality of memory cells positioned side-by-side on the substrate, each of the memory cells having a floating gate and a control gate which overlies the floating gate, source regions formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions.

5. The memory cell array of claim 1 wherein electron tunneling paths are formed between the first edge portions of the floating gates and portions of the source regions are overlapped by the first edge portions.

6. The memory cell array of claim 1 wherein the bit lines are positioned beneath the select gates, and two select gates transistors are formed with each of the bit lines and the select gate above it.

7. The memory cell array of claim 1 wherein a hot carrier path for the injection of electrons during a program operation is formed from a mid-channel region in the substrate between the select gate and the floating gate, to the floating gate, with high voltage coupling between the control gate and the floating gate.

8. The memory cell array of claim 1 including means for applying a negative voltage to the control gates of unselected memory cells to turn off the floating gate transistors in those cells during program and read operations.

2. In a memory cell array:

a substrate, a plurality of memory cells positioned side-by-side on the substrate, each of the memory cells having a floating gate and a control gate which overlies the floating gate, the floating gates being wider than the control gates and having first and second edge portions which project laterally beyond the edges of the control gates, source regions formed in the substrate between and partially overlapped by the first edge portions of the floating gates in adjacent ones of the cells, bit lines formed in the substrate midway between the second edge portions of the floating gates in adjacent ones of the cells, and a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions.

3. The memory cell array of claim 2 wherein the laterally projecting edge portions of the floating gates are sharply rounded.

4. The memory cell array of claim 3 wherein the select gates have side walls which face the sharply rounded lateral edges of the floating gates, and electron tunneling paths are formed between the sharply rounded lateral edge portions of the floating gates and the side walls of the select gates.

9. In a memory cell array:

a substrate, a plurality of memory cells positioned side-by-side on the substrate, each of the memory cells having a floating gate and a control gate which overlies the floating gate, the floating gates being wider and substantially thinner than the control gates and having first and second sharply rounded edge portions which project laterally beyond the edges of the control gates, source regions formed in the substrate between and partially overlapped by the first edge portions of the floating gates in adjacent ones of the cells, bit lines formed in the substrate between the second edge portions of the floating gates in adjacent ones of the cells, and a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions.

10. The memory cell array of claim 9 wherein the floating gate has a thickness on the order of 100-1000Å

, and the control gate has a thickness on the order of 1500-3500Å

.

11. The memory cell array of claim 9 wherein the bit lines are positioned midway between the second edge portions of the floating gates.

12. In a memory cell array:

a substrate, a plurality of memory cells positioned side-by-side on the substrate, each of the memory cells having a floating gate and a control gate which overlies the floating gate, source regions formed in the substrate between and partially overlapped by the first edge portions of the floating gates in adjacent ones of the cells, bit lines formed in the substrate midway between the second edge portions of the floating gates in adjacent ones of the cells, a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions, and dielectric material between the floating gate and the control gate and between the control gate and the select gate, the dielectric material between the floating gate and the control gate being substantially thinner than the dielectric material between the control gate and the select gate.

13. The memory cell of claim 12 wherein the dielectric material between the floating gate and the control gate has a thickness on the order of 120Å

-500Å

, and the dielectric material between the control gate and the select gate has a thickness on the order of 1000Å

-3000Å

.

14. The memory cell array of claim 12 wherein the bit lines are positioned midway between the second edge portions of the floating gates.