Semiconductor memory

• US 6,426,909 B1
• Filed: 08/09/2001
• Issued: 07/30/2002
• Est. Priority Date: 11/17/2000
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Tomita, Hiroyoshi
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/924,779
• Publication Number:
  US 20020060940A1
• Time in Patent Office: 355 Days
• Field of Search: 365/222, 365/230.03, 365/230.06, 365/230.08, 365/233, 365/236
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

The refresh circuit generates a refresh request for refreshing memory cells at a predetermined interval. The refresh counter generates a refresh address. The holding circuit respectively holds information as to the completion/incompletion of refresh of the memory cells in each of the banks, the memory cells being designated by the refresh address. The refresh control circuit refreshes bank(s) yet to be refreshed among the banks not in operation upon the occurrence of the refresh request, based on the information held in the holding circuit. That is, under a single refresh address, banks yet to be refreshed are successively refreshed every time refresh request occurs. The refresh operations are performed on banks that are not in operation. Therefore, the refresh operations can be performed without being recognized from exterior. That is, the semiconductor memory having a plurality of banks can perform the refresh of memory cells internally and automatically.

Claims

1. A semiconductor memory comprising:

a plurality of banks each having memory cells;

a refresh circuit for generating a refresh request for refreshing said memory cells, at a predetermined interval;

a refresh counter for generating a refresh address and supplying it to said plurality of banks;

a holding circuit for holding information about completion/incompletion of refreshing said memory cells in each of said banks; and

a refresh control circuit for refreshing the bank which does not operate and is in the incompletion status in response to said refresh request, based on said information held in said holding circuit.

2. The semiconductor memory according to claim 1, wherein

when all of said information held in said holding circuit indicates completion, said holding circuit changes said all information to incompletion and said refresh counter counts up.

3. The semiconductor memory according to claim 1, wherein

a maximum time available for consecutive access to each of said banks is specified to be shorter than the interval of occurrence of said refresh request.

4. The semiconductor memory according to claim 1, comprising

a priority circuit for determining one of said plurality of banks to be refreshed when said banks not in operation include a plurality of banks yet to be refreshed.

5. A semiconductor memory comprising:

a plurality of banks each having memory cells;

a refresh circuit for generating a refresh request for refreshing said memory cells, at a predetermined interval;

an address generating circuit for generating a plurality of refresh addresses;

a plurality of holding circuits for respectively holding information about completion/incompletion of refreshing said memory cells designated by each of said refresh addresses in each of said banks; and

a refresh control circuit for refreshing the banks which do not operate and are in the incompletion status in response to said refresh request, based on said information held in each of said holding circuits.

6. The semiconductor memory according to claim 5, wherein said address generating circuit comprises:

a refresh counter for generating one of said refresh addresses; and

an address holding circuit for holding the refresh address previously generated by said refresh counter.

7. The semiconductor memory according to claim 6, wherein when all of said information held in one of said holding circuits corresponding to said address holding circuit indicates completion,

one of said holding circuits corresponding to said refresh counter changes said all information to incompletion after transferring said held information to said holding circuit corresponding to said address holding circuit and

said refresh counter counts up after transferring a current counter value to said address holding circuit.

8. The semiconductor memory according to claim 6, wherein

a maximum time available for consecutive access to each of said banks is specified to be shorter than

 

(interval at which refresh request occurs)×

(number of banks)×

(number of holding circuits−

1).

9. The semiconductor memory according to claim 5, comprising

a priority circuit for determining one of said memory cells to be refreshed when said banks not in operation include a plurality of said memory cells yet to be refreshed corresponding to said refresh address.