Memory device having a variable data output length and a programmable register

• US 6,426,916 B2
• Filed: 02/27/2001
• Issued: 07/30/2002
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US09/796,206
• Publication Number:
  US 20010009276A1
• Time in Patent Office: 518 Days
• Field of Search: 365/233, 365/194, 365/189.01, 365/233.5
• US Class Current: 365/233.1
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing a value which is representative of a number of cycles of an external clock signal to transpire after which the memory device responds to a read request. The method further includes providing block size information to the memory device, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes receiving the amount of data, after the number of clock cycles of the external clock signal transpire.

Claims

1. A method of operation of a synchronous memory device, wherein the memory device includes an array of memory cells, the method of operation of the memory device comprises:

receiving a value that is representative of a number of cycles of an external clock signal to transpire after which the memory device responds to a first operation code;

receiving block size information, wherein the block size information is representative of an amount of data to be output by the memory device in response to the first operation code;

sampling the first operation code synchronously with respect to a transition of the external clock signal; and

outputting the amount of data, in response to the first operation code, after the number of clock cycles of the external clock signal transpire.

2. The method of claim 1 wherein the amount of data is output synchronously with respect to the external clock signal.

3. The method of claim 1 wherein a first portion of the amount of data is output synchronously with respect to a rising edge transition of the external clock signal and a second portion of the amount of data is output synchronously with respect to a falling edge transition of the external clock signal.

4. The method of claim 1 wherein the block size information is further representative of an amount of data to be input by the memory device in response to a second operation code, the method further including:

receiving the second operation code synchronously with respect to the external clock signal; and

receiving the amount of data to be input by the memory device.

5. The method of claim 1 further including receiving address information to identify at least one memory cell in the array of memory cells.

6. The method of claim 5 wherein the address information, the amount of data, and the first operation code are received in a multiplexed format over a set of external signal lines.

7. The method of claim 6 wherein the first operation code is included in a request packet.

8. The method of claim 7 wherein the request packet includes the address information.

9. The method of claim 1 wherein the first operation code includes precharge information.

10. The method of claim 1 wherein the amount of data is output onto an external bus synchronously with respect to the external clock signal.

11. The method of claim 10 wherein the external bus includes a plurality of signal lines that carries multiplexed control and address information.

12. The method of claim 1 wherein the block size information is sampled synchronously with respect to a transition of the external clock signal.

13. The method of claim 1 wherein the block size information is a binary code.

14. The method of claim 1 further including receiving a third operation code, wherein in response to the third operation code, the value that is representative of a number of cycles of the external clock signal to transpire is stored in a register located on the memory device.

15. A method of controlling a synchronous memory device by a controller, wherein the memory device includes an array of memory cells, the method of controlling the memory device comprises:

providing a value to the memory device, wherein the value is representative of a number of cycles of an external clock signal to transpire after which the memory device responds to a first operation code;

providing block size information to the memory device, wherein the block size information is representative of an amount of data to be output by the memory device in response to the first operation code; and

providing the first operation code to the memory device, wherein the first operation code instructs the memory device to perform a read operation, wherein, in response to the first operation code, the memory device outputs the amount of data after the number of cycles of the external clock signal transpire.

16. The method of claim 15 wherein the block size information is further representative of an amount of data to be input by the memory device in response to a second operation code and wherein the method further includes:

providing the second operation code to the memory device, wherein the second operation code instructs the memory to input the amount of data; and

providing, to the memory device, the amount of data to be input by the memory device.

17. The method of claim 16 wherein the amount of data to be input is sampled by the memory device, in response to the second operation code, after a delay time transpires.

18. The method of claim 16 wherein a first portion of the amount of data is issued to the memory device synchronously with respect to a rising edge transition of the external clock signal and a second portion of the amount of data is issued to the memory device synchronously with respect to a falling edge transition of the external clock signal.

19. The method of claim 15 further including providing a third operation code to the memory device, wherein the third operation code instructs the memory device to store the value in a programmable register.

20. The method of claim 15 further including receiving the amount of data output by the memory device in response to the first operation code.

21. The method of claim 15 wherein the first operation code is provided to the memory device in a request packet.

22. The method of claim 21 wherein the block size information and the first operation code are both provided to the memory device in the request packet.

23. The method of claim 15 wherein the first operation code and the block size information are provided to the memory device via an external bus.

24. The method of claim 23 wherein the block size information, address information and the first operation code are multiplexed over a set of signal lines of the external bus.

25. The method of claim 15 wherein the block size information is a binary code.

26. A synchronous semiconductor memory device having at least one memory section including a plurality of memory cells, the memory device comprising:

clock receiver circuitry to receive an external clock signal;

first input receiver circuitry to sample block size information synchronously with respect to the external clock signal, wherein the block size information is representative of an amount of data to be output by the memory device in response to a first operation code;

a register which stores a value that is representative of an amount of time to transpire after which the memory device outputs the first amount of data; and

a plurality of output drivers to output the amount of data in response to the first operation code and after the amount of time transpires.

27. The memory device of claim 26 wherein the first input receiver circuitry samples the value synchronously with respect to the external clock signal.

28. The memory device of claim 26 wherein in response to a second operation code, the value is stored in the register.

29. The memory device of claim 28 further including second input receiver circuitry to sample the second operation code synchronously with respect to the external clock signal.

30. The memory device of claim 26 wherein the amount of data is output synchronously with respect to the external clock signal.

31. The memory device of claim 26 wherein a first portion of the amount of data is output synchronously with respect to a rising edge transition of the external clock signal and a second portion of the amount of data is output synchronously with respect to a falling edge transition of the external clock signal.

32. The memory device of claim 26 further including second input receiver circuitry to sample the first operation code synchronously with respect to the external clock signal.

33. The memory device of claim 32 wherein the block size information and the first operation code are included in a request packet.

34. The memory device of claim 33 wherein the first input receiver circuitry and the second input receiver circuitry couple to an external bus.

35. The memory device of claim 26 wherein the plurality of output drivers output the amount of data onto an external bus.

36. The memory device of claim 35 wherein the external bus includes a plurality of signal lines to carry multiplexed control information, address information and data.

37. The memory device of claim 26 wherein the first input receiver circuitry samples address information synchronously with respect to the external clock signal.

38. The memory device of claim 37 wherein the first input receiver circuitry couples to an external bus, and wherein the external bus includes a plurality of signal lines to carry the address information and the amount of data in a multiplexed format.

39. The memory device of claim 26 wherein the value is a binary code.

40. The memory device of claim 26 further including delay lock loop circuitry, coupled to the clock receiver circuitry, to generate an internal clock signal, wherein the plurality of output drivers output the amount of data in response to the internal clock signal.

41. The method of claim 26 wherein the block size information is a binary code.