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Separate code and data contexts: an architectural approach to virtual text sharing

  • US 6,427,162 B1
  • Filed: 05/02/1996
  • Issued: 07/30/2002
  • Est. Priority Date: 05/02/1996
  • Status: Expired due to Term
First Claim
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1. A processor comprising:

  • a processing unit for processing requests from at least one process, said at least one process having a code portion with at least one code segment, said at least one code segment having a first code context identifier, said process further having a data portion with at least one data segment having a first data context identifier;

    a code address translation look aside buffer (CTLB) for storing code address translations, the CTLB having at least one entry for storing a virtual address, said first code context identifier, and a physical address;

    a data storage device for storing data address translations;

    a code context register, coupled to said processing unit and to said CTLB, for storing a second code context identifier;

    a data context register, coupled to said processing unit and to said data storage device for storing a second data context identifier; and

    a code context comparing unit for comparing said first code context identifier with said second code context identifier and responsive to the comparison for generating a code context hit signal, wherein said CTLB includes a single entry for process segments having the same virtual address and the same process context identifier.

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