Separate code and data contexts: an architectural approach to virtual text sharing
First Claim
1. A processor comprising:
- a processing unit for processing requests from at least one process, said at least one process having a code portion with at least one code segment, said at least one code segment having a first code context identifier, said process further having a data portion with at least one data segment having a first data context identifier;
a code address translation look aside buffer (CTLB) for storing code address translations, the CTLB having at least one entry for storing a virtual address, said first code context identifier, and a physical address;
a data storage device for storing data address translations;
a code context register, coupled to said processing unit and to said CTLB, for storing a second code context identifier;
a data context register, coupled to said processing unit and to said data storage device for storing a second data context identifier; and
a code context comparing unit for comparing said first code context identifier with said second code context identifier and responsive to the comparison for generating a code context hit signal, wherein said CTLB includes a single entry for process segments having the same virtual address and the same process context identifier.
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Accused Products
Abstract
The present invention provides a processor including a core unit for processing requests from at least one process. The at least one process has a code portion with at least one segment having a first code context identifier. The at least one process also has a data portion with a first data context identifier. The processor further includes a first storage device for storing code address translations and a second storage device for storing data address translations. The processor also includes a code context register coupled to the core unit and to the first storage device, for storing a second code context register. The processor also includes a data context register, coupled to the core unit and to the second storage device for storing a second data context identifier.
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Citations
6 Claims
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1. A processor comprising:
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a processing unit for processing requests from at least one process, said at least one process having a code portion with at least one code segment, said at least one code segment having a first code context identifier, said process further having a data portion with at least one data segment having a first data context identifier;
a code address translation look aside buffer (CTLB) for storing code address translations, the CTLB having at least one entry for storing a virtual address, said first code context identifier, and a physical address;
a data storage device for storing data address translations;
a code context register, coupled to said processing unit and to said CTLB, for storing a second code context identifier;
a data context register, coupled to said processing unit and to said data storage device for storing a second data context identifier; and
a code context comparing unit for comparing said first code context identifier with said second code context identifier and responsive to the comparison for generating a code context hit signal, wherein said CTLB includes a single entry for process segments having the same virtual address and the same process context identifier.
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2. A computer system comprising:
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a bus;
a memory device coupled to said bus; and
a processor coupled to said bus said processor including a core unit for processing requests from at least one process, said process having a code portion with at least one code segment, said at least one code segment having a first code context identifier, said process further having a data portion with a first data context identifier;
a code address translation look aside buffer (CTLB) for storing code address translations, the CTLB having at least one entry for storing a virtual address, said first code context identifier, and a physical address;
a second storage device for storing data address translations;
a code context register, coupled to said core unit and to said first storage device, for storing a second code context identifier;
a data context register, coupled to said core unit and to said second storage device for storing a second data context identifier; and
a code context comparing unit for comparing said first code context identifier with said second code context identifier and responsive to the comparison for generating a code context hit signal, wherein said CTLB includes a single entry for process segments having the same virtual address and the same process context identifier.
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3. In a computer system including a processor having a code context register, a data context register, a code translation look aside buffer (CTLB), a data translation look aside buffer (DTLB), and a virtual address register, a computer-implemented method for sharing virtual address translation resources by a plurality of processes having code and data segments, the method comprising the steps of:
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mapping each of said processes code and data segments into an address space;
allocating for each of said processes a data sub-address space context identifier;
determining whether a first process can share code segments with other processes having a common code sub-address space context identifier;
if said first process can share code segments with said other processes, assigning said first process said common code sub-address space context identifier; and
if said process cannot share code segments with said other processes having a common code sub-address space context identifier, assigning said first process a unique code sub-address space context identifier. - View Dependent Claims (4, 5)
loading a code context register with a current context identifier and loading a virtual register with a current virtual address; - and
determining whether said CTLB has an entry including said current context identifier and said current virtual address.
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5. The method of claim 4 further including the step of
finding a translation entry in a kernel translation data structure including said current code context identifier and said current virtual address, if said CTLB does not have an entry including said current context identifier and said current virtual address; - and
loading said translation entry in said CTLB.
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6. A computer system comprising:
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a first process having a code segment with a first code context identifier and having a data segment with a first data context identifier;
a second process having a code segment with a second code context identifier and having a data segment with a second data context identifier; and
the first process and the second process have a common code context identifier when the first process and second process share a same text object.
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Specification