Electronic system and method for display using a decoder and arbiter to selectively allow access to a shared memory

• US 6,427,194 B1
• Filed: 03/30/2000
• Issued: 07/30/2002
• Est. Priority Date: 08/26/1996
• Status: Expired due to Term

• Current Assignee: Parthenon Unified Memory Architecture LLC (Acacia Research Corporation)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV), STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Colavin, Osvaldo, Owen, Jefferson Eugene, Diaz, Raul Zegers
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US09/539,729
• Time in Patent Office: 852 Days
• Field of Search: 711/151, 711/147, 711/158, 710/68, 710/113, 710/119, 710/22, 709/247, 345/511, 345/512, 345/202, 345/519, 345/535, 345/541
• US Class Current: 711/151
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/427 Display on the fly, e.g. simultaneous writing to and reading from decoding memory
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/443 OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02

Abstract

An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Claims

1. A portion of an electronic system for coupling to a memory and a display device, the portion of the electronic system comprising:

a first bus communicatively linked to the memory to allow access for the display device, subject to a display device access control, through the first bus to the memory without also requiring a second bus to access the memory;

a decoder communicatively linked to the first bus for receiving compressed images and displaying decoded images on the display device and to access the memory, subject to a decoder access control, through the first bus without also requiring a second bus to access the memory, the memory storing at least one previously decoded image used to decode a current image, the memory being a region of a main memory of the electronic system; and

an arbiter wherein the arbiter is communicatively linked to the display device for the display device access control, the arbiter communicatively linked to the decoder for the decoder access control, the arbiter configured to control access to the memory for the display device and the decoder.

2. The portion of the electronic system of claim 1, further comprising a memory interface, the memory interface being communicatively linked to the decoder and to the first bus, the arbiter being monolithically integrated with the memory interface.

3. The portion of the electronic system of claim 1, further comprising a memory interface, the memory interface being communicatively linked to the display device and the memory, the arbiter being monolithically integrated with the memory interface.

4. The portion of the electronic system of claim 1, wherein the arbiter comprises a cell or device separate from any monolithic integration of the display device or decoder.

5. The portion of the electronic system of claim 1 wherein the decoder comprises a video decoder.

6. The portion of the electronic system of claim 1 wherein the decoder is configured to decode a bitstream formatted to comply with the MPEG-2 standard.

7. The portion of the electronic system of claim 1, wherein the arbiter controls access to the memory for at least the display device and the decoder based upon requests from the display device and from the decoder to access the memory.

8. The portion of the electronic system of claim 1 wherein the first bus comprises either a PCI bus or a memory bus.

9. The portion of the electronic system of claim 1, further comprising an encoder communicatively linked to the first bus, subject to an encoder access control, to access the memory through the first bus without also requiring a second bus to access the memory, the arbiter communicatively linked to the encoder for the encoder access control, the arbiter configured to control access to the memory for the encoder.

10. The portion of the electronic system of claim 9 wherein the encoder is configured to produce a bitstream that complies with the H.263 standard.

11. A computer comprising:

a first bus;

a display device communicatively linked to the first bus;

a decoder communicatively linked to the first bus for receiving compressed images, for decoding the compressed images into decoded images and for displaying the decoded images on the display device;

a memory interface communicatively linked to the first bus, the memory interface comprising an arbiter; and

a memory communicatively linked to the memory interface such that the display device and the decoder have access to the memory without requiring a second bus for the display device or the decoder to access the memory, the access of the display device and the decoder to the memory being controlled by the arbiter based at least upon requests of the display device and the decoder to access the memory, the memory storing at least one previously decoded image used to decode a current image, the memory being a region of a main memory of the computer accessible through the first bus.

12. The computer of claim 11 wherein the display device is either a chipset or a graphics accelerator.

13. The computer of claim 11 wherein the first bus is either a PCI bus or a memory bus.

14. The computer of claim 11 wherein the decoder directly supplies a display adapter of the display device with an image for use other than decoding a subsequent image.

15. The computer of claim 11 wherein the memory stores intra images obtained from other than a preceding image and stores predicted images obtained from a preceding image, the images directly supplied to the display adapter being bidirectional images obtained from two preceding intra and predicted images.

16. An electronic system comprising:

a first bus for coupling to a display device;

a memory communicatively linked to the first bus to allow access for the display device, subject to a display device access control, through the first bus to the memory without also requiring a second bus to access the memory, the electronic system storing at least one previously decoded image used to decode a current image;

a decoder communicatively linked to the first bus for receiving compressed images from the memory and for decoding the compressed images into decoded images to be displayed on the display device, subject to a decoder access control, without also requiring a second bus to access the memory; and

an arbiter communicatively linked to the display device for the display device access control, the arbiter communicatively linked to the decoder for the decoder access control, the arbiter configured to control access to the integrated circuit memory for the display device and the decoder.

17. An electronic system comprising:

a first bus for coupling to a display device;

a memory communicatively linked to the first bus to allow access for the display device, subject to a display device access control, through the first bus to the memory without also requiring a second bus to access the memory, the electronic system storing at least one previously decoded image used to decode a current image;

a decoder communicatively linked to the first bus for receiving compressed images from the memory and for decoding the compressed images into decoded images to be displayed on the display device, subject to a decoder access control, without also requiring a second bus to access the memory; and

an encoder communicatively linked to the bus, subject to an encoder access control, to access the memory through the first bus without also requiring a second bus to access the memory, the arbiter communicatively linked to the encoder for the encoder access control, the arbiter configured to control access to the memory for the encoder.

18. An electronic system comprising:

a first bus;

a memory communicatively linked to the first bus;

a first device incorporated into the electronic system, the first device communicatively linked to the first bus to access the memory, subject to a first device access control, through the first bus to the memory without also requiring a second bus to access the memory;

a decoder communicatively linked to the first bus to access the memory, subject to a decoder access control, through the first bus to the memory without also requiring a second bus to access the memory; and

an arbiter communicatively linked to the first device for the first device access control, the arbiter communicatively linked to the decoder for the decoder access control, the arbiter configured to control access to the memory for the first device and the decoder.

19. The electronic system of claim 18, wherein the decoder is monolithically integrated into the first device.

20. The electronic system of claim 18 wherein the decoder comprises a video decoder.

21. The electronic system of claim 18 wherein the decoder is configured to decode a bitstream formatted to comply with the MPEG-2 standard.

22. The electronic system of claim 18 wherein the arbiter controls access to the memory for at least the first device and the decoder based upon requests from the first device and from the decoder to access the integrated circuit memory.

23. The electronic system of claim 18, further comprising an encoder communicatively linked to the first bus, subject to an encoder access control, to access the memory through the first bus without also requiring a second bus to access the memory, the arbiter communicatively linked to the encoder for the encoder access control, the arbiter configured to control access to the memory for the encoder.

24. The electronic system of claim 23 wherein the encoder is configured to produce a bitstream that complies with the H.263 standard.

25. A method comprising:

storing in a memory at least one previously decoded image used to decode a current image;

allowing access for a display device, subject to a display device access control, through a first bus to the memory;

receiving compressed images from the memory at a decoder and for decoding the compressed images by the decoder into decoded images to be displayed on the display device, subject to a decoder access control, without also requiring a second bus to access the memory; and

communicatively linking an arbiter to the decoder for the decoder access control and to the display device for display device access control, the arbiter configured to control access to the memory for the display device and the decoder.