SRAM controller for parallel processor architecture including address and command queue and arbiter

• US 6,427,196 B1
• Filed: 08/31/1999
• Issued: 07/30/2002
• Est. Priority Date: 08/31/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wolrich, Gilbert, Cutter, Daniel, Wheeler, William, Adiletta, Matthew J., Redfield, James
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US09/387,110
• Time in Patent Office: 1,064 Days
• Field of Search: 711/104, 711/105, 711/151, 711/158, 711/168, 711/169, 710/39, 710/52, 710/54, 710/57, 710/112, 712/233
• US Class Current: 711/158
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

A controller for a random access memory includes an address and command queue that holds memory references from a plurality of micro control functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Claims

1. A controller for a random access memory said controller comprising:

an address and command queue that holds memory references from a plurality of microcontrol functional units, said address and command queue comprising;

a read queue;

a first read/write queue that holds memory references from a core processor; and

control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

2. The controller of claim 1 wherein the control logic further selects a memory reference from one of the queues to provide a next memory reference based on a programmable value stored in a priority service control register.

3. The controller of claim 1 wherein the address and command queue further comprises:

a high priority queue that holds memory references from high priority tasks.

4. The controller of claim 1 wherein a microengine sorts memory references into read and write memory references.

5. The controller of claim 1 wherein the address and command queue further comprises:

an order queue that holds write memory requests wherein the controller examines incoming memory reference requests and sorts the incoming memory reference requests into either the read queue or the order queue in accordance with a specified address mode.

6. The controller of claim 1 wherein the address and command queue comprises:

an order queue; and

wherein if the memory reference request does not have a memory optimization bit set, the memory reference request is stored in the order queue.

7. The controller of claim 1 wherein the address and command queue is implemented in a single memory structure and further comprises:

an order queue for storing memory references;

the read queue for storing memory references;

a high priority queue for storing memory references; and

with the memory structure being segmented into four different queue regions, each region having its own head and tail pointer.

8. The controller of claim 7 wherein the address and command queue further comprises:

an insert queue control and a remove queue arbitration logic to control insert and removal respectively of memory references from the queues.

9. The controller of claim 1 further comprising:

a command decoder and address generator that is responsive to an address from a selected memory reference from one of the queues, to produce addresses and commands to control a memory interface.

11. The controller of claim 9 wherein controller further comprises:

a lock lookup content addressable memory for look-ups of read locks.

17. The controller of claim 1 wherein the controller is configured to control static random access memory (SRAM).

10. The controller of claim i further comprising:

a memory interface responsive to generated addresses and commands to produce memory control signals.

12. The controller of claim 10 wherein the address and command queue further comprises:

a Read Lock Fail Queue to hold read lock memory reference requests that fail because of a preexisting lock on a portion of a random access memory controlled by the controller.

13. The controller of claim 12 wherein the command decoder responds if one of the microengines issues a read lock request by accessing the lock lookup memory to determine whether a memory location specified in the read lock request is already locked.

14. The controller of claim 13 wherein if the memory location is locked from any prior read lock request, then the issued memory lock request fails and is stored in the read lock fail queue.

15. The controller of claim 14 wherein if the memory location is not locked then the issued read reference is converted into address signals for the memory by the memory interface.

16. The controller of claim 15 wherein the command decoder and address generator enters the lock for the memory address for the issued read reference into the lock look up memory.