Accurate high speed digital signal processor

• US 6,427,203 B1
• Filed: 08/22/2000
• Issued: 07/30/2002
• Est. Priority Date: 06/04/1996
• Status: Expired due to Term

• Current Assignee: V-Silicon Semiconductors (HEFEI) Co., Ltd.
• Original Assignee: Sigma Designs Incorporated
• Inventors: Le Cornec, Yann
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/643,373
• Time in Patent Office: 707 Days
• Field of Search: 712/24, 712/210, 712/212, 712/220, 712/221, 712/35, 712/23, 712/36, 712/25, 712/34, 712/26, 712/222, 712/223, 712/224, 712/225, 712/227, 712/228, 712/213, 708/204, 708/505, 708/503, 708/497, 708/523, 708/632, 708/490, 708/508, 708/494, 708/510, 708/631
• US Class Current: 712/35
• CPC Class Codes: G06F 7/49963 Rounding to nearest G06F7/49957 takes precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter

Abstract

An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions with look-ahead rounding, so that rounding after repeated arithmetic operations proceeds much more rapidly. The digital signal processor is also augmented with additional instruction formats which are particularly useful for digital signal processing. A first additional instruction format allows the digital signal processor to incorporate a small constant immediately into an instruction, such as to add a small constant value to a register value, or to multiply a register by a small constant value; this allows the digital signal processor to conduct the arithmetic operation with only one memory lookup instead of two. A second additional instruction format allows the digital signal processor to loop back to a location relatively addressed from the looping instructions; this allows the digital signal processor to conduct the loop operation with only one memory lookup instead of two.

Claims

1. A memory, including a set of instructions, wherein said set of instructions are executable by a digital signal processor, said digital signal processor having an instruction decoder coupled to an instructions memory for decoding said set of instruction fetched from said instruction memory, said digital signal processor being responsive to a short-immediate instruction wordsaid set of instructions comprising:

coupling an accumulator register to output of an arithmetic processing unit;

coupling a round value into said accumulator register;

loading said rounding into said accumulator register substantially contemporaneously with start an arithmetic operation of said arithmetic processing unit;

selecting an arithmetic operation to be performed responsive to an opcode field in said short immediate instruction word; and

selecting an immediate constant as an operand for said arithmetic operation to be performed, said immediate constant being responsive only to an immediate field in said short immediate instruction word, said immediate constant being substantially different from a binary value represent by said immediate field.

2. A memory as in claim 1, said memory coupled to an instruction decoder for decoding said set of instructions fetched from said memory;

said digital signal processor being responsive to a loop relative instruction work, said set of instructions including;

defining a program fragment to be executed repeatedly, said means being responsive to an offset field in said loop-relative instruction word, said offset field representing a binary value substantially equal to a length of said program fragment;

defining a count of a number of times said program fragment is to be executed; and

repeatedly executing said program fragment, said means being operative to adjust a program counter in said digital signal processor by said binary value.

3. A memory, including a set of instruction, wherein said set of instruction are executable by a digital signal processor, said set to an instruction comprising instruction for coupling said digital signal processor to an instruction memory for decoding a plurality of instruction fetched from said instruction memory, said instruction including:

defining a short-immediate instruction word in said instruction memory;

selecting an arithmetic operation to be performed responsive to an opcode field in said short-immediate instruction word; and

selecting an immediate constant as an operand for said arithmetic operation to be performed, said immediate constant being responsive only to an immediate field in said short immediate instruction work, said immediate constant being substantially different from a binary value represented by said immediate field;

wherein said immediate constant comprises a single bit having a first logic value and a plurality of bits having a second logic value, said single bit being selected in response to a binary value represented by a first portion of said immediate field when a second portion of said immediate field has a first selected value, and

wherein said immediate constant comprises a single bit having a said second logic value and a plurality of bits having said first logic value, said single bit being selected in response to a binary value represented by said first portion of said immediate field when said second portion of said immediate field has a second selected value.

4. A memory, including a set of instructions, wherein said set of instructions are executable by a digital signal processor, said set of instructions including coupling said digital signal processor to an instruction memory for decoding a plurality of instructions fetched from said instruction memory, including instructions of:

defining a short-immediate instruction word in said instruction memory;

selecting an arithmetic operation to be performed responsive to an opcode field in said short-immediate instruction word; and

selecting an immediate constant as an operand for said arithmetic operation to be performed, said immediate constant being responsive only to an immediate field in said short immediate instruction work, said immediate constant being substantially different from a binary value represented by said immediate field;

wherein said immediate constant comprises a single bit having a first logic value and a plurality of bits having a second logic value, said single bit being selected in response to a binary value represented by a first portion of said immediate field when a second portion of said immediate field has a first selected value, and

wherein said immediate constant comprises a single bit having a said second logic value and a plurality of bits having said first logic value, said single bit being selected in response to a binary value represented by said first portion of said immediate field when said second portion of said immediate field has a second selected value.

5. A memory as in claim 4, wherein said immediate field comprises a variable-length first portion and a variable-length second portion, said first portion and second portion collectively comprising the entire immediate field

wherein said immediate constant is substantially equal to a positive binary value represented by said second portion when said first portion has a first selected value;

wherein said immediate constant is substantially equal to a negative binary value represented by said second portion when said first portion has a second selected value;

wherein said immediate constant comprises a single bit having a first logic value and a plurality of bits having a second logic value, said single bit being selected in response to a binary value represented by said second portion when said first portion has a third selected value; and

wherein said immediate constant comprises a single bit having said second logic value and a plurality of bits having said first logic value, said single bit being selected in response to a binary value represented by said second portion when said first portion has a fourth selected value.