Backside illumination of CMOS image sensor

• US 6,429,036 B1
• Filed: 01/14/2000
• Issued: 08/06/2002
• Est. Priority Date: 01/14/1999
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Doudoumopoulos, Nicholas, Nixon, Robert, Fossum, Eric R.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LATTIN, CHRISTOPHER W
• Application Number:
  US09/483,362
• Time in Patent Office: 935 Days
• Field of Search: 438/108, 438/125, 438/455, 438/408, 438/66, 438/67, 438/459, 438/460, 438/57, 438/60
• US Class Current: 438/57
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A CMOS image sensor die is fabricated and packaged to allow the light sensitive area of the die to be illuminated from either the front side or the backside, or both. The implementation is achieved using wafer level processing that facilitates photon collection at both surfaces. This approach permits processing apt the wafer level to allow the deposition of color filter arrays (CFA) on either surface. The silicon is thinned and the bump contacts and interconnect lines are relocated away from the image area of the die. The die is covered with an optically transparent material to provide additional support.

Claims

1. A method of manufacturing an image sensor comprising:

attaching a first cover layer to an active surface of a silicon wafer;

attaching a second cover layer to an opposite surface of the silicon wafer;

notching the silicon wafer along the second cover layer; and

forming electrical interconnections on the notched surface of the silicon wafer;

wherein the image sensor is light sensitive from a back side.

2. The method of claim 1, wherein the electrical interconnections comprise bump contacts.

3. The method of claim 1, wherein the electrical interconnections comprise interconnect lines.

4. The method of claim 1, wherein the electrical interconnections are formed away from the active surface of the silicon wafer.

5. The method of claim 1, further comprising the steps of:

grinding the silicon wafer from the opposite surface of the silicon wafer; and

dicing the wafer into individual dies.

6. The method of claim 5, wherein the individual dies have a thickness in the range of approximately 0.6 mm to approximately 2.0 mm.

7. The method of claim 1, further comprising coating the second glass surface with a color filter layer.

8. The method of claim 7, wherein the filter layer is a color filter array.

9. The method of claim 8, wherein the electrical interconnections are formed on the first glass surface.

10. The method of claim 1, wherein the image sensor is light sensitive from a front side.

11. The method of claim 1, wherein the electrical interconnections are located outside an image area.