Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface

• US 6,429,128 B1
• Filed: 07/12/2001
• Issued: 08/06/2002
• Est. Priority Date: 07/12/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Besser, Paul Raymond, Ngo, Minh Van, Zhao, Larry
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/902,587
• Time in Patent Office: 390 Days
• Field of Search: 438/687, 438/627, 438/628, 438/629, 438/643, 438/644, 438/653, 438/654, 438/678
• US Class Current: 438/687
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76862 Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu at a reduced RF power, e.g., about 400 to about 500 watts and an increased spacing, e.g., about 680 to about 720 mils, to reduce the compressive stress of the deposited silicon nitride layer to below about 2×10⁷ Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NH₃ diluted with N₂, ramping up the introduction of SiH₄ and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure and N₂ flow rate during plasma treatment, SiH₄ ramp up and silicon nitride deposition. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

introducing a wafer containing inlaid copper (Cu) or a Cu alloy into a chamber;

treating an exposed surface of the Cu or Cu alloy to remove oxide therefrom;

depositing a silicon nitride capping layer on the treated Cu or Cu alloy surface by plasma enhanced chemical vapor deposition (PECVD); and

controlling conditions during PECVD such that the deposited silicon nitride capping layer has a compressive stress no greater than about 2×

10⁷ Pascals.

2. The method according to claim 1, comprising controlling conditions during PECVD, such that the deposited silicon nitride layer has a density of about 2.67 to about 2.77 g/cm³.

3. The method according to claim 1, comprising depositing the silicon nitride layer at an RF power of about 400 to about 500 watts.

4. The method according to claim 3, comprising depositing the silicon nitride layer at a spacing of about 680 to about 720 mils.

5. The method according to claim 4, comprising depositing the silicon nitride layer at a deposition rate no greater than about 34 Å

/sec.

6. The method according to claim 5, comprising depositing the silicon nitride layer at:

a silane (SiH_y) flow rate of about 130 to about 170 sccm;

an ammonia (NH₃) flow rate of about 250 to about 310 sccm; and

a nitrogen (N₂) flow rate of about 8,000 to about 9,000 sccm.

7. The method according to claim 1, wherein

the wafer contains a dual damascene structure comprising a Cu or Cu alloy line in contact with an underlying Cu or Cu alloy via formed in a dielectric layer;

and

the dielectric layer comprises a material having a dielectric constant less than about 3.9.

8. The method according to claim 4, comprising treating the exposed Cu or Cu alloy surface with a plasma containing NH₃ and N₂ to remove the oxide therefrom.

9. The method according to claim 8, comprising the sequential steps:

(a) introducing the wafer into a chamber;

(b) treating the exposed surface of the Cu or Cu alloy with a plasma containing NH₃ and N₂ in the chamber at a pressure;

(c) introducing SiH₄ into the chamber; and

(d) depositing the silicon nitride capping layer on the surface of the Cu or Cu alloy in the chamber, the method comprising conducting steps (c) and (d) while substantially maintaining the pressure used in step (b).

10. The method according to claim 9, comprising conducting step (c) by introducing SiH₄ into the chamber in two stages.

11. The method according to claim 10, wherein step (c) comprises the sequential stages:

(c₁) introducing SiH₄ at a flow rate of about 70 to about 90 sccm; and

(c₂) increasing the flow rate of silane to about 130 to about 170 sccm before initiating deposition of the silicon nitride capping layer.

12. The method according to claim 11, wherein:

step (a) further comprises;

generating a N₂ flow rate of about 8,000 to about 9,000 sccm;

generating an NH₃ flow rate of about 210 to about 310 sccm;

elevating the temperature to about 300°

C.; and

elevating the pressure to about 3 to about 5 Torr; and

step (b) comprises treating the surface of the Cu or Cu alloy with the plasma containing NH₃ at an RF power of about 50 to about 200 watts and a temperature of about 300°

C. to about 400°

C.

13. The method according to claim 12, comprising conducting:

step (a) for about 10 to about 15 seconds;

step (b) for about 5 to about 40 seconds;

stage (c₁) for about 2 to about 3 seconds; and

stage (c₂) for about 3 to about 8 seconds.

14. The method according to claim 4, comprising depositing the silicon nitride capping layer at a thickness of about 450 Å

to about 550 Å

.

15. A method of manufacturing a semiconductor device, the method comprising the following sequential steps:

(a) introducing a wafer containing a copper (Cu) or Cu alloy interconnect into a deposition chamber, introducing nitrogen (N₂) at a flow rate of about 8,000 to about 9,200 sccm, introducing ammonia (NH₃) at a flow rate of about 210 to about 310 sccm, elevating the temperature and elevating the pressure;

(b) generating a plasma at a RF power of about 50 to about 200 watts, pressure of about 3 to about 5 Torr and temperature of about 300°

C. to about 400°

C., and treating an exposed surface of the Cu or Cu alloy interconnect with a plasma containing NH₃ and N₂;

(c) gradually introducing silane (SiH₄) into the deposition chamber, while maintaining the pressure at about 3 to about 5 Torr, in the following sequential stages;

(c₁) introducing (SiH₄) at a flow rate of about 70 to about 90 sccm; and

(C2) increasing the flow rate of SiH₄ to about 130 to about 170 sccm; and

(f) generating a plasma at an RF power of about 400 to about 500 watts and depositing a layer of silicon nitride on the Cu or Cu alloy surface in the deposition chamber at a spacing of about 680 to about 720 mils while maintaining the pressure at about 3 to about 5 Torr, wherein the deposited silicon nitride layer has a compressive stress no greater than about 2×

10⁷ Pascals and a density of about 2.67 to about 2.77 g/cm³.

16. The method according to claim 15, comprising conducting steps (c) and (d) while maintaining the N₂ flow rate at about 8,000 to about 9,200 sccm and while maintaining the NH₃ flow rate at about 250 to about 310 sccm.

17. The method according to claim 15, comprising depositing the silicon nitride layer at a deposition rate of no greater than about 34 Å

/sec.

18. The method according to claim 15, comprising depositing the silicon nitride capping layer at a thickness of about 450 Å

to about 550 Å

.

19. The method according to claim 15, wherein the wafer comprises a dual damascene structure comprising a Cu or Cu alloy line in contact with an underlying Cu or Cu alloy via formed in a dielectric layer.

20. The method according to claim 19, wherein the dielectric layer comprises a dielectric material having a dielectric constant less than about 3.9.