Anisotropic formation process of oxide layers for vertical transistors

• US 6,429,148 B1
• Filed: 10/09/2001
• Issued: 08/06/2002
• Est. Priority Date: 10/09/2001
• Status: Expired due to Term

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: Chu, Yu-Ping, Chu, Yu-Wen
• Primary Examiner(s): Thompson, Craig
• Application Number:
  US09/971,735
• Time in Patent Office: 301 Days
• Field of Search: 438/766, 438/758, 438/770, 438/795-799, 438/800
• US Class Current: 438/766
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02299 pre-treatment
• CPC Class Codes: H01L 21/2822 with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical

Abstract

The method of the present invention forms a thin oxide layer on the circumferential wall of a recess in a trench and, at the same time, forms a thick oxide layer on the bottom surface of the recess. The thick oxide layer serves as the trench top oxide and the thin oxide layer serves as the gate oxide.

Claims

1. A method for forming a thick oxide layer on a bottom surface of a recess and a thin oxide layer on a circumferential wall of said recess, wherein said recess is a part of a trench formed in a substrate, and said circumferential wall is perpendicular to said bottom surface, comprising the steps of:

implanting inert gas ions into said bottom surface at a direction parallel to said circumferential wall; and

thermally processing said substrate by a thermal oxidation process to form said thick oxide layer on said bottom surface and said thin oxide layer on said circumferential wall.

2. The method of claim 1, wherein said inert gas is selected from a group consisting of neon (Ne), argon (Ar) and krypton (Kr).

3. The method of claim 1, wherein said inert gas is argon.

4. The method of claim 1, wherein said recess is located above a trench capacitor, and said bottom surface of said trench is on a top surface of a buried strap.

5. The method of claim 1, wherein said thick oxide layer is a trench top oxide of a trench capacitor.

6. The method of claim 1, wherein said thin oxide layer is a gate oxide of a vertical transistor.

7. The method of claim 1, wherein said inert gas ion is implanted at an energy level ranging from about 5 to 100 keV.

8. The method of claim 7, wherein said energy level is about 15 to 40 keV.