CMOS imager with storage capacitor
First Claim
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1. A CMOS imager system comprising:
- (i) a processor; and
(ii) a CMOS imaging device coupled to said processor, said CMOS imaging system comprising;
a doped layer of a first conductivity type formed in a substrate;
a charge collection region formed in said doped layer;
a first doped region of a second conductivity type formed in said doped layer adjacent to said charge collection region;
a storage capacitor; and
a contact connecting said first doped region to said storage capacitor.
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Abstract
A CMOS imager having an improved signal to noise ratio and improved dynamic range is disclosed. The CMOS imager provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager. The storage capacitor may be a flat plate capacitor formed over the pixel,a stacked capacitor or a trench imager formed in the photosensor. The CMOS imager thus exhibits a better signal-to-noise ratio and improved dynamic range. Also disclosed are processes for forming the CMOS imager.
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Citations
53 Claims
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1. A CMOS imager system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor, said CMOS imaging system comprising;
a doped layer of a first conductivity type formed in a substrate;
a charge collection region formed in said doped layer;
a first doped region of a second conductivity type formed in said doped layer adjacent to said charge collection region;
a storage capacitor; and
a contact connecting said first doped region to said storage capacitor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A CMOS imager system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor, said CMOS imaging system comprising;
a doped layer of a first conductivity type formed in a substrate;
a charge collection region formed in said doped layer;
a first doped region of a second conductivity type formed in said doped layer adjacent to said charge collection region; and
a trench storage capacitor formed in said substrate adjacent to said first doped region and connected to said first doped region to store charge collected in said charge collection region. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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Specification