Multiple active layer structure and a method of making such a structure

• US 6,429,484 B1
• Filed: 08/07/2000
• Issued: 08/06/2002
• Est. Priority Date: 08/07/2000
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yu, Bin
• Primary Examiner(s): Ngô, Ngân V.
• Application Number:
  US09/633,208
• Time in Patent Office: 729 Days
• Field of Search: 257/67, 257/347, 257/353, 257/354
• US Class Current: 257/347
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

An integrated circuit includes multiple active layers. Preferably, a semiconductor-on-insulator (SOI) or silicon-on-insulator wafer is utilized to house a first active layer. A second active layer is provided above an insulative layer above the SOI substrate. Solid phase epitaxy can be used to form the second active layer. Subsequent active layers can be added by a similar technique. A seeding window can also be utilized.

Claims

1. An integrated circuit, comprising:

a semiconductor-on-insulator layer including a first active layer and a first insulating layer, the first active layer containing a first channel region between a pair of first source/drain regions and being disposed above the first insulating layer;

a second active layer containing a second channel region between a pair of second source/drain regions; and

a second insulating layer being disposed between the second active layer and the first active layer, the second insulating layer including a seeding window, the seeding window being filled with material from the second active layer, thereby connecting one of the first sources drain regions to one of the second source/drain regions, wherein the one of the first source/drain regions is directly aligned with and below the one of the second source/drain regions.

2. The integrated circuit of claim 1, wherein the second active layer is formed via solid phase epitaxy.

3. The integrated circuit of claim 2, wherein the first active layer is physically connected to the second active layer through the seeding window.

4. The integrated circuit of claim 1, wherein the first active layer and the second active layer are each less than 500 Å

thick.

5. The integrated circuit of claim 1 further comprising:

a third insulating layer above the second active layer; and

a third active layer above the third insulating layer.

6. The integrated circuit of claim 5, wherein the third active layer is physically connected to the second active layer through a second seeding window, the second seeding window being disposed through the third insulating layer.

7. The integrated circuit of claim 6, wherein the third active layer includes third source/drain regions and one of the third source/drain regions is coupled through the second seeding window to the one second source/drain region, the second seeding window being aligned with the first seeding window.

8. A multilayer structure for containing a plurality of transistors, the multilayer structure comprising:

a first layer including an oxide layer, a first active semiconductor layer, and a first insulating layer, the oxide layer being disposed below the first active layer, the first active layer being disposed below the first insulating layer;

a second active layer disposed above the first insulating layer, the second active layer being recrystallized through a first seeding window in the first insulating layer, the second active layer being disposed below a second insulating layer; and

a third active layer disposed above the second insulating layer, the third active layer being recrystallized through a second seeding window is aligned with respect to the first seeding window, wherein at least one transistor is at least partially disposed in the first active layer and at least another transistor is disposed a least partially in the second active layer wherein at least a further transistor is being disposed, at least partially in the third active layer.

9. The multilayer structure of claim 8, wherein a conductive via is disposed through the first insulating layer, the conductive via being electrically coupled to the first active layer and the second active layer.

10. The multilayer structure of claim 8 further comprising a second insulating layer disposed above the second active layer.

11. The multilayer structure of claim 10, wherein the second active layer is formed from an amorphous silicon layer.

12. The multilayer structure of claim 8, wherein the first layer and the second active layer crystallographically communicate through the first seeding window.

13. The multilayer structure of claim 10, wherein the third active layer is crystallographically communicates through the second seeding window.

14. The multilayer structure of claim 8 further comprising a substrate disposed below the oxide layer.

15. A semiconductor-on-insulator integrated circuit including a first active layer and a first insulating layer, the first active layer containing a first channel region and being disposed above the first insulating layer, a second active layer containing a second channel region, and a second insulating layer being disposed between the second active layer and the first active layer, the second insulating layer including a first seeding window, wherein the integrated circuit further involves a third active layer containing a third channel region, the third active layer being above a thin insulative layer having a second seeding window, the second seeding window being above the first seeding window, is manufactured by:

providing the semiconductor-on-insulator substrate;

providing the second insulating layer over the semiconductor-on-insulator substrate;

providing the first seeding window in the second insulating layer; and

forming a single crystalline semiconductor layer above the first insulating layer for the second active layer.

16. The integrated circuit of claim 15, wherein the forming step includes depositing an amorphous silicon layer.

17. The integrated circuit of claim 16, wherein the amorphous silicon layer is heated to form the single crystalline semiconductor layer.

18. The integrated circuit of claim 17 further comprising depositing the third insulating layer over the single crystalline semiconductor layer.

19. The integrated circuit of claim 18 further comprising:

forming the second seeding window through the third insulating layer; and

forming a second single crystalline semiconductor layer above the second insulating layer.

20. The integrated circuit of claim 15, wherein the forming step utilizes a laser anneal or very low temperature furnace anneal.