Semiconductor device having gate to body connection

• US 6,429,487 B1
• Filed: 01/08/2001
• Issued: 08/06/2002
• Est. Priority Date: 07/18/2000
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kunikiyo, Tatsuya
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HO, TU TU V
• Application Number:
  US09/755,118
• Publication Number:
  US 20020027246A1
• Time in Patent Office: 575 Days
• Field of Search: 257/347, 257/409, 257/354
• US Class Current: 257/354
• CPC Class Codes: H01L 29/783 comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET for thin film transistors H01L29/78612, H01L29/78696
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

In an isolation region of an SOI substrate (1), an STI (10) is formed in a silicon layer (4). In an end portion of the isolation region, a p⁺-type impurity diffusion region (11) is selectively formed, being buried in part of an upper surface of the STI (10), in an upper surface of the silicon layer (4). In an element formation region of the SOI substrate (1), a body region (15) which is in contact with a side surface of the impurity diffusion region (11) is formed in the silicon layer (4). A tungsten plug (14) is in contact with the impurity diffusion region (11) with a barrier film (13) interposed therebetween, and in contact with part of an upper surface of a gate electrode (9) and a side surface thereof with the barrier film (13) interposed therebetween. With this structure obtained is a semiconductor device which makes it possible to avoid or suppress generation of an area penalty which is generated when a gate-body contact region is formed inside the silicon layer in an SOI-DTMOSFET.

Claims

1. A semiconductor device comprising:

an SOI substrate of multilayered structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order;

an isolation insulating film formed in said semiconductor layer in an isolation region of said SOI substrate;

a body region selectively formed in said semiconductor layer in an element formation region of said SOI substrate defined by said isolation insulating film;

a gate electrode formed on said body region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said isolation insulating film and said gate electrode;

a contact hole so selectively formed in said interlayer insulating film as to expose part of said gate electrode and overlap in plane view part of said isolation insulating film; and

a connection body including a conductor formed in said contact hole, for electrically connecting said gate electrode and said body region, wherein at least part of a bottom surface of said connection body is in contact with said isolation insulating film.

2. The semiconductor device according to claim 1, wherein

said conductor is a metal plug.

3. The semiconductor device according to claim 1, wherein

said conductor is a semiconductor in which an impurity is introduced.

4. The semiconductor device according to claim 1, wherein

said isolation insulating film is a full-isolation insulating film formed extending from an upper surface of said semiconductor layer to an upper surface of said insulating layer.

5. The semiconductor device according to claim 1, wherein

said isolation insulating film is a partial-isolation insulating film having a bottom surface which does not reach an upper surface of said insulating layer.

6. The semiconductor device according to claim 1, further comprising:

a sidewall formed on a side surface of said gate electrode.

7. The semiconductor device according to claim 1, wherein

the whole of said bottom surface of said connection body overlaps said isolation insulating film below said contact hole.

8. The semiconductor device according to claim 1, wherein

part of said bottom surface of said connection body overlaps said isolation insulating film below said contact hole.

9. The semiconductor device according to claim 8, wherein

said contact hole is formed above an upper surface of said semiconductor layer.

10. The semiconductor device according to claim 9, wherein

said gate electrode has a first semiconductor layer of a first conductivity type, and

said connection body has a second semiconductor layer of a second conductivity type which is different from said first conductivity type,

said semiconductor device further comprising an insulating film formed between said first semiconductor layer and said second semiconductor layer.

11. The semiconductor device according to claim 1, further comprising

a barrier film formed in an interface between said connection body and said body region.

12. The semiconductor device according to claim 1, wherein

said gate electrode is a gate electrode having light transmissivity.

13. A semiconductor device comprising:

an SOI substrate of multilayered structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order, having a first element formation region and a second element formation region which are isolated from each other by an isolation region;

an isolation insulating film formed in said semiconductor layer in said isolation region;

a first semiconductor element formed in said first element formation region, having a first body region selectively formed in said semiconductor layer and a first gate electrode formed on said first body region with a first gate insulating film interposed therebetween;

a second semiconductor element formed in said second element formation region, having a second body region selectively formed in said semiconductor layer and a second gate electrode formed on said second body region with a second gate insulating film interposed therebetween;

an interlayer insulating film covering said isolation insulating film and said first and second gate electrodes;

a contact hole so selectively formed in said interlayer insulating film as to expose part of said first gate electrode and part of said second gate electrode; and

a connection body including a conductor formed in said contact hole, for electrically connecting said first and second gate electrodes and said first and second body regions.

14. The semiconductor device according to claim 13, wherein

at least part of a bottom surface of said connection body overlaps in plane view said isolation insulating film.

15. The semiconductor device according to claim 14, wherein

the whole of said bottom surface of said connection body overlaps said isolation insulating film.

16. A semiconductor device comprising:

an SOI substrate of multilayered structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order;

an isolation insulating film formed in said semiconductor layer in an isolation region of said SOI substrate;

a body region selectively formed in said semiconductor layer in an element formation region of said SOI substrate defined by said isolation insulating film;

a gate electrode formed on said body region with a gate insulating film interposed therebetween; and

bias generation means connected between said body region and said gate electrode, for limiting a body voltage which is to be applied to said body region to 0.6 V or lower.

17. The semiconductor device according to claim 16, further comprising:

an interlayer insulating film covering said isolation insulating film and said gate electrode;

a contact hole so selectively formed in said interlayer insulating film as to expose part of said gate electrode and overlap in plane view part of said isolation insulating film; and

a connection body including a conductor formed in said contact hole, being connected to said body region,

wherein at least part of a bottom surface of said connection body overlaps in plane view said isolation insulating film below said contact hole.

18. The semiconductor device according to claim 17, further comprising:

a sidewall made of an insulating film for preventing said gate electrode and said conductor from coming into electrical contact.