Digital fractional phase detector

• US 6,429,693 B1
• Filed: 06/30/2000
• Issued: 08/06/2002
• Est. Priority Date: 06/30/2000
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Leipold, Dirk, Staszewski, Robert B.
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/608,317
• Time in Patent Office: 767 Days
• Field of Search: 327/2, 327/3, 327/113, 327/117, 327/156, 327/158, 327/159, 327/12, 327/105, 327/106, 327/107
• US Class Current: 327/12
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.

Claims

1. A digital fractional phase detector comprising:

a time-to-digital converter (TDC) having a plurality of delay elements associated with a first input and a plurality of latch/register elements associated wit both a second input and a plurality of outputs, wherein the fist input is configured to receive a first clock signal, and further wherein the second input is configured to receive a reference clock signal such that the plurality of latch/register elements store a snapshot of a delayed replica vector of first clock signal data in response to significant edge transitions associated with the reference clock signal; and

a digital edge detector having a plurality of inputs in communication with the plurality of outputs, and fixer having first and second outputs, wherein the edge detector is responsive to the delayed replica vector of first clock data such that the fist output generates a TDC rse-time signal associated with timing of a positive transition of the first clock signal and further wherein the edge detector is responsive to the stream of first clock state data such that the second output generates a TDC fall-dine signal associated with timing of a negative transition of the fist clock signal.

2. The digital fractional phase detector according to claim 1 further comprising a normalizer element having a first input configured to receive the TDC rise-time signal and further having a second input configured to receive the TDC fall-time signal, wherein the normalizer element is responsive to the TDC rise-time signal and the TDC fall-time signal to generate a period-normalized fractional phase signal that is normalized by a clock period associated with the first clock signal.

3. The digital fractional phase detector according to claim 2 further comprising a combinatorial element configured to combine the period-normalized fractional phase signal with an accumulated frequency control word fractional phase signal and generate a fractional phase compensated signal therefrom.

4. The digital fractional phase detector according to claim 1 wherein the plurality of delay elements comprise inverters.

5. The digital fractional phase detector according to claim 4 wherein the first clock signal is associated with a numerically-controlled voltage controlled oscillator.

6. The digital fractional phase detector according to claim 1 wherein the plurality of delay elements are selected from the group consisting of buffers, a tapped delay line, and inverters.

7. The digital fractional phase detector according to claim 1 wherein the digital fractional phase detector is configured to increase overall resolution of an integer phase-locked loop (PLL) such that a quantization error e of the integer PLL will be corrected.

8. The digital fractional phase detector according to claim 1 further comprising a digital edge detector in communication with the plurality of latch/register elements and configured to generate a first time-to-digital signal associated with a timing of a first transition of the first clock and further configured to generate a second time-to-digital signal associated with a timing of a second transition of the first clock.

9. A digital fractional phase detector comprising:

a first input configured to receive a first clock signal;

a plurality of delay elements in communication with the first input;

a second input configured to receive a second clock signal;

a plural of latch/registers in communication with the plurality of delay elements and the second input such that the plurality of latch/registers store a delayed replica of fist clock signal data in response to significant edge transitions associated with the second clock signal;

a digital edge detector in communication with the plurality of latch/registers and configured to generate a time-to-digital rise-time signal associated with a timing of a positive transition of the first clock signal and further configured to generate a time-to digital fall-time signal associated with a timing of a negative transition of the first clock;

a normalizer element responsive to the rise-time signal and the fall-time signal to generate a period-normalized fractional phase signal that is normalized to a clock period associated with the first clock signal; and

an output, wherein the digital factional phase detector is responsive to the first and second clock signals such that it generates a fractional phase compensated signal therefrom at the output, wherein the fractional phase compensated signal affects a zero averaged phase difference between the first clock signal and the second clock signal.

10. The digital fractional phase detector according to claim 9 wherein the plurality of delay elements comprise inverters.

11. The digital fractional phase detector according to claim 9 wherein the plurality of delay elements are selected from the group consisting of buffers, a tapped delay line, and inverters.

12. The digital fractional phase detector according to claim 9 further comprising a combinatorial element configured to combine the period-normalized fractional phase signal with an accumulated frequency control word fractional phase signal and generate a fractional phase compensated signal therefrom.

13. The digital fractional phase detector according to claim 12 wherein the first clock signal is associated with a numerically-controlled voltage controlled oscillator.

14. The digital fractional phase detector according to claim 13 wherein the second clock signal is associated with a frequency reference oscilator.

15. The digital fractional phase detector according to claim 9 wherein the first clock signal is associated with a numerically-controlled voltage controlled oscillator.

16. The digital fractional phase detector according to claim 15 wherein the second clock signal is associated with a frequency reference oscillator.

17. The digital fractional phase detector according to claim 9 wherein the digital fractional phase detector is configured to increase overall resolution of an integer phase-locked loop (PLL) such that a quantization error ε

of the integer PLL will be corrected.

18. A digital factional phase detector comprising:

means for receiving a digitally-controlled voltage controlled oscillator (dVCO) clock signal;

means for receiving a frequency reference clock signal and storing a snapshot of a delayed replica of said dVCO clock signal data in response to significant edge transitions associated with the frequency reference clock signal;

means for retrieving the delayed replica of said dVCO clock signal data in response to the frequency reference clock signal and generating a rise-time sign and a fall-time signal therefrom; and

means for receiving the rise-time signal and the fall-time signal and generating a period-normalized fractional phase signal therefrom.

19. The digital fractional phase detector according to claim 18 further comprising means for combining the period-normalized fractional phase signal with an accumulated frequency control word fractional phase signal to generate a fractional phase compensated signal therefrom.

20. A digital fractional phase detector comprising:

first means for receiving a first clock signal, wherein the first receiving means comprises a plurality of delay elements selected from the group consisting of inverters, a tapped delay line, and buffers;

second means for receiving a second clock signal, wherein the second receiving means comprises a plurality of latch/registers and coupled to said first means for storing a delayed replica of said first clock signal;

a digital edge detecting means responsive to said first and second means for generating a rise-time signal associated with a positive transition of the first clock and further for generating a fall-time signal associated with a negative transition of the first clock; and

means for receiving an accumulated frequency control word fractional phase signal and said rise-time and fall-time signals to generate a fractional phase compensated signal therefrom.

21. The digital fractional phase detector according to claim 20 wherein the first clock signal is associated with a digitally-controlled voltage controlled oscillator (dVCO).

22. The digital fractional phase detector according to claim 21 wherein the second clock is associated with a frequency reference oscillator.

23. A digital fractional phase detector comprising:

a plurality of delay elements connected in tandem, wherein each delay element has an input and an output, and further wherein the first delay element input is a VCO clock input;

a plurality of latch/registers, wherein each latch/register has a first input connected to an output of a different delay element, and further wherein each latch/register has a second input configured to receive a common frequency reference clock signal, and further wherein each latch/register has an output;

a digital edge detector having a plurality of inputs, wherein each edge detector input is connected to a different latch/register output, and further having a pair of outputs;

a normalizer element having a pair of inputs connected to the pair of edge detector outputs, and further having an output; and

a combinatorial element having an input connected to the output of the normalizer element and further having an output.

24. The digital fractional phase detector according to claim 23 wherein the plurality of delay elements are selected from the group consisting of inverters, a tapped delay line, and buffers.

25. The digital fractional phase detector according to claim 24 wherein the digital fractional phase detector is configured to increase overall resolution of an integer phase-locked loop (PLL) such that a quantization error c of the integer PLL is corrected.

26. A digital factional phase detector comprising:

means for receiving a digitally-controlled voltage controlled oscillator (dVCO) clock signal;

means for receiving a frequency reference clock signal and storing a snapshot of a delayed replica of said dVCO clock signal data in response to significant edge transitions associated with the frequency reference clock signal;

means for retrieving the delayed replica of said dVCO clock signal data in response to the frequency reference clock signal and generating a fit time-to-digital signal and a second time-to-digital signal therefrom; and

means for receiving the first time-to-digital signal and the second time-to-digital signal and generating period-normalized factional phase signal therefrom.

27. The digital fractional phase detector according to, claim 26 further comprising means for receiving the first time-to-digital signal and the second time-to-digital signal and generating a period-normalized fractional phase signal therefrom.

28. The digital fractional phase detector according to claim 27 further comprising means for combining the period-normalized fractional phase signal with an accumulated frequency control word fractional phase signal to generate a fractional phase compensated signal therefrom.

29. The digital fractional phase detector according to claim 28 wherein the digital fractional phase detector is configured to increase overall resolution of an integer phase-locked loop (PLL) such that a quantization error ε

of the integer PLL is corrected.