RMS-DC converter using a variable gain amplifier to drive a squaring cell

• US 6,429,720 B1
• Filed: 05/12/2000
• Issued: 08/06/2002
• Est. Priority Date: 05/12/2000
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Gilbert, Barrie
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US09/569,544
• Time in Patent Office: 816 Days
• Field of Search: 327/346, 327/348, 327/355, 327/356, 327/358, 327/359
• US Class Current: 327/348
• CPC Class Codes: G01R 19/02 Measuring effective values, i.e. root-mean-square values
• CPC Class Codes: G05F 3/222 with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: G05F 3/265 using bipolar transistors only
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated

Abstract

An RMS-DC converter provides extended dynamic range by driving a squaring cell with a variable gain amplifier. Temperature effects in the squaring cell can be cancelled by driving a second squaring cell with a reference signal and averaging the difference between the output signals from the two squaring cells. In a transmission system utilizing a power measurement system having two detector cells, square-law conformance errors in the detector cells can be cancelled by driving one of the detectors cells with a replica of the baseband modulation signal.

Claims

1. An RMS-DC converter comprising:

a variable gain amplifier having a input port and an output port;

a squaring cell having an input port coupled to the output port of the variable gain amplifier; and

an averaging circuit coupled to an output port of the squaring cell.

2. An RMS-DC converter according to claim 1 wherein the squaring cell is a transconductance cell.

3. An RMS-DC converter according to claim 1 wherein the averaging circuit performs short-term ripple filtering and long-term averaging.

4. An RMS-DC converter comprising:

a variable gain amplifier having an input port and an output port;

a squaring cell having an input port coupled to the output port of the variable gain amplifier; and

an averaging circuit coupled to an output port of the squaring cell;

wherein the averaging circuit integrates the difference between a squared signal from the squaring cell and a reference signal.

5. An RMS-DC converter comprising:

a variable gain amplifier having an input port and an output port;

a squaring cell having an input port coupled to the output port of the variable gain amplifier; and

an averaging circuit coupled to an output port of the squaring cell;

wherein the variable gain amplifier comprises a continuously interpolated attenuator.

6. An RMS-DC converter comprising:

a variable gain amplifier having an input port and an output port;

a squaring cell having an input port coupled to the output port of the variable gain amplifier; and

an averaging circuit coupled to an output port of the squaring cell;

wherein the variable gain amplifier has exponential gain control.

7. An RMS-DC converter comprising:

a variable gain amplifier having an input port and an output port;

a squaring cell having an input port coupled to the output port of the variable gain amplifier; and

an averaging circuit coupled to an output port of the squaring cell;

wherein the averaging circuit has an output port coupled back to a gain control input of the variable gain amplifier.

8. An RMS-DC converter comprising:

a variable gain amplifier having a input port and an output port;

a first detector cell having in input port coupled to the output port of the variable gain amplifier;

a second detector cell; and

an averaging circuit coupled to the first and second detector cells.

9. An RMS-DC converter according to claim 8 wherein the detector cells are squaring cells.

10. An RMS-DC converter according to claim 9 wherein the squaring cells are a transconductance cells.

11. An RMS-DC converter according to claim 8 wherein the averaging circuit performs short-term ripple filtering and long-term averaging.

12. An RMS-DC converter according to claim 8 wherein the averaging circuit integrates the difference between a squared signal from the first detector cell and a reference signal from the second detector cell.

13. An RMS-DC converter according to claim 8 wherein the variable gain amplifier comprises a continuously interpolated attenuator.

14. An RMS-DC converter according to claim 8 wherein the variable gain amplifier has exponential gain control.

15. A method for performing an RMS-DC conversion comprising:

driving a squaring cell with a variable gain amplifier, thereby generating a squared signal; and

averaging the squared signal, thereby generating an output signal.

16. A method for performing an RMS-DC conversion comprising:

driving a squaring cell with a variable gain amplifier, thereby generating a squared signal;

averaging the squared signal, thereby generating an output signal; and

comparing the squared signal to a reference signal.

17. A method for performing an RMS-DC conversion comprising:

driving a squaring cell with a variable gain amplifier, thereby generating a squared signal;

averaging the squared signal, thereby generating an output signal; and

controlling the gain of the variable gain amplifier responsive to the output signal.

18. A method for performing an RMS-DC conversion comprising:

driving a squaring cell with a variable gain amplifier, thereby generating a squared signal;

averaging the squared signal, thereby generating an output signal;

controlling a device responsive to the output signal;

utilizing an output signal from the device as the input signal; and

controlling the gain of the variable gain amplifier responsive to a set-point signal.

19. A method for performing an RMS-DC conversion comprising:

driving a variable gain amplifier responsive to a first input signal;

driving a first detector cell with the variable gain amplifier, thereby generating a first output signal;

driving a second detector cell responsive to a second input signal, thereby generating a second output signal; and

averaging the difference between the first output signal and the second output signal, thereby generating a final output signal.

20. A method according to claim 19 wherein the second input signal is a reference signal.

21. A method according to claim 20 further comprising adjusting the reference signal, thereby compensating for noise.

22. A method according to claim 19 further comprising controlling the gain of the variable gain amplifier responsive to the final output signal.

23. A method according to claim 19 further comprising:

controlling a device responsive to the final output signal;

utilizing an output signal from the device as the first input signal; and

controlling the gain of the variable gain amplifier responsive to a set-point signal.

24. A method according to claim 23 wherein the second input signal is a modulation signal, and further comprising driving the device with a carrier signal modulated by the modulation signal.

25. A method according to claim 19 further comprising:

controlling a device responsive to the final output signal;

utilizing an output signal from the device as the second input signal; and

controlling the gain of the variable gain amplifier responsive to a set-point signal.

26. A method according to claim 25 wherein the first input signal is a modulation signal, and further comprising driving the device with a carrier signal modulated by the modulation signal.

27. A method for performing an RMS-DC conversion comprising:

driving a first detector cell responsive to a modulation signal;

driving a second detector cell responsive to a carrier signal that is modulated by the modulation signal; and

averaging the difference between an output signal from the first detector cell and an output signal from the second detector cell.

28. An RF transmission system comprising:

a power amplifier for amplifying an RF carrier signal;

an antenna coupled to the power amplifier;

a coupler coupled to the antenna for sampling the power transmitted by the system;

a first detector cell coupled to the coupler;

an averaging circuit coupled between the first detector cell and the power amplifier; and

a second detector cell coupled to the averaging circuit for receiving a modulation signal.

29. A system according to claim 28 further comprising a variable gain amplifier coupled between the coupler and the first detector cell.

30. A system according to claim 28 further comprising a variable gain amplifier coupled to the second detector cell for amplifying the modulation signal.

31. A method for controlling the power of a modulated RF carrier signal transmitted from a system having a power amplifier coupled to an antenna, the method comprising:

sampling the modulated RF carrier signal transmitted from the system, thereby generating a sampled signal;

driving a first detector cell responsive to the sampled signal;

driving a second detector cell responsive to a modulation signal used to modulate the RF carrier signal;

averaging the difference between an output signal from the first detector cell and an output signal from the second detector cell, thereby generating an output signal; and

controlling the gain of the power amplifier responsive to the output signal.

32. A method according to claim 31 further comprising amplifying the sampled signal responsive to a gain control signal.

33. A method according to claim 31 further comprising amplifying the modulation signal responsive to a gain control signal.

34. An RMS-DC converter system comprising:

a variable gain amplifier having a input port and an output port;

a squaring cell having an input port coupled to the output port of the variable gain amplifier; and

an averaging circuit coupled to an output port of the squaring cell;

wherein the variable gain amplifier has an input system comprising;

an attenuator coupled to the input port for receiving an input signal and a plurality of tap ports for generating a plurality of attenuated signals responsive to the input signal; and

a plurality of gm stages, each gm stage coupled to one of the tap ports to receive one of the attenuated signals;

wherein each of the gm stages includes a transistor cell for generating two output currents responsive to the attenuated signal, and a node for receiving one of a plurality of interpolator signals for controlling the gain of the transistor cell; and

wherein a first one of the output currents from each gm stage is coupled to an AC ground.

35. A system according to claim 34 wherein each gm stage further includes a filter coupled to the node.

36. A system according to claim 34 wherein the second output currents from the gm stages are combined to generate a first main output signal, and wherein the system further includes a compensation transistor coupled to a common terminal of the attenuator to generate a second main output signal responsive to the common mode voltage of the common terminal.

37. A system according to claim 34 wherein:

the second output currents from the gm stages are combined to generate a first main output signal;

each gm stage further includes a compensation transistor coupled to a corresponding one of the tap ports for generating a third output current responsive to the common mode voltage of the tap port; and

the third output currents from the gm stages are combined to generate a second main output signal.

38. A system according to claim 37 wherein each gm stage further includes a filter coupled to the compensation transistor.

39. A system according to claim 37 wherein each gm stage further includes means for turning the compensation transistor completely off when the corresponding interpolator signal is substantially off.

40. A system according to claim 34 wherein the second output currents from the gm stages are combined to generate a first main output signal, and further including a cascode stage coupled to receive the first main output signal.

41. A system according to claim 37 further including a cascode stage coupled to receive the first and second main output signals.

42. A system according to claim 34 wherein:

the input impedance of the attenuator at the input port is relatively high;

the input port of the attenuator includes first and second input terminals;

the first input terminal is coupled to a first pin through a first bondwire to receive the input signal;

the second input terminal is coupled to a second pin through a second bondwire; and

the system further includes a termination impedance coupled between the first and second pins.

43. A system according to claim 34 wherein each gm stage further includes means for turning the gm stage completely off when the corresponding interpolator signal is substantially off.

44. A system according to claim 43 wherein the means for turning the gm stage completely off includes a current source coupled to the node to cancel a portion of the interpolator signal.

45. A system according to claim 44 wherein the means for turning the gm stage completely off further includes a resistor coupled between the current source and the node to provide a defined reverse bias to the transistor cell.

46. A system according to claim 43 wherein the means for turning the gm stage completely off includes a resistor coupled between the node and a power supply terminal.

47. A system according to claim 46 wherein the means for turning the gm stage completely off further includes a diode coupled between the node and an input terminal of one of the transistors of the transistor cell to prevent excessive reverse bias on the one transistor.

48. A system according to claim 34 wherein:

each tap port of the attenuator includes a first tap point; and

each transistor cell includes a first transistor having a base coupled to the first tap point of the corresponding tap port, an emitter coupled to the node, and a collector coupled to an AC ground for coupling the first output current thereto.

49. A system according to claim 48 wherein each transistor cell further includes a second transistor having a base coupled to an AC ground, an emitter coupled to the node, and a collector coupled an output bus for coupling the second output current thereto.

50. A system according to claim 49 wherein the base of the second transistor of each transistor cell is coupled to receive a feedback signal.

51. A system according to claim 49 wherein each gm stage further includes a capacitor coupled between the node and an AC ground.

52. A system according to claim 49 wherein each gm stage further includes a resistor coupled between the node and an AC ground.

53. A system according to claim 49 wherein each gm stage further includes a third transistor having a base coupled to the base of the second transistor, an emitter coupled to receive one of a second plurality of interpolator signals, and a collector coupled to a second output bus.

54. A system according to claim 53 further including:

a first cascode transistor coupled to the first output bus; and

a second cascode transistor coupled to the second output bus.

55. A system according to claim 53 wherein the second and third transistors of each gm stage have the same collector-junction capacitance.

56. A system according to claim 49 wherein:

each tap port of the attenuator includes a second tap point that is AC grounded;

the base of the second transistor in each gm stage is coupled to the second tap point of the corresponding tap port; and

the first and second tap points of each tap port are located physically close.

57. A system according to claim 56 wherein the second tap points of the attenuator are coupled together at a heavy-duty bus bar which forms the bottom of the attenuator.

58. An RMS-DC converter system comprising:

a variable gain amplifier having a input port and an output port;

a squaring cell having an input port coupled to the output port of the variable gain amplifier; and

an averaging circuit coupled to an output port of the squaring cell;

wherein the variable gain amplifier comprises;

an intermediate stage;

an output stage coupled to the intermediate stage; and

a feedback network coupled between the output stage and the intermediate stage.

59. A system according to claim 58 wherein the feedback network comprises a capacitor arranged to compensate for the capacitance of a transistor in the intermediate stage.

60. A system according to claim 59 wherein the feedback network further comprises a second capacitor arranged to compensate for the capacitance of a second transistor in the intermediate stage.

61. A system according to claim 58 wherein the feedback network comprises a resistor arranged to compensate for the Early voltage of a transistor in the intermediate stage.

62. A system according to claim 61 wherein the feedback network comprises a second resistor arranged to compensate for the Early voltage of a second transistor in the intermediate stage.

63. An RMS-DC converter system comprising:

a variable gain amplifier having a input port and an output port;

a squaring cell having an input port coupled to the output port of the variable gain amplifier; and

an averaging circuit coupled to an output port of the squaring cell;

wherein the squaring cell comprises;

a first exponential current generator for generating a first current responsive to an input signal; and

a second exponential current generator for generating a second current responsive to the input signal;

wherein the first and second exponential current generators are coupled together to combine the first and second currents;

wherein each of the exponential current generators comprises a constant current stack coupled to a first input terminal, and a variable current stack coupled to a second input terminal and the constant current stack;

wherein each constant current stack comprises a first emitter-follower transistor coupled to a first input terminal, a diode-connected transistor coupled to the emitter follower transistor, and a current source coupled to the diode-connected transistor;

wherein each variable current stack comprises a second emitter-follower transistor coupled to a second input terminal, and a fourth transistor coupled between the second emitter-follower transistor and the diode-connected transistor; and

wherein each constant current stack further comprises a resistor coupled between the base and collector of the diode-connected transistor.

64. A system according to claim 63 wherein each variable current stack further comprises a second resistor coupled between the second emitterfollower transistor and the fourth transistor.