Integrated circuit with charge pump and method

• US 6,429,723 B1
• Filed: 09/11/2000
• Issued: 08/06/2002
• Est. Priority Date: 11/18/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hastings, Roy A.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US09/658,776
• Time in Patent Office: 694 Days
• Field of Search: 327/535, 327/536, 327/537, 363/59, 363/60, 307/110
• US Class Current: 327/536
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/077 with parallel connected charge pump stages

Abstract

An integrated circuit comprises a first node (11) and a first stage charge pump (510) coupled to the first node (11) and to load circuitry (520). The first stage charge pump comprises a first capacitor (C1) coupled to a first signal source (φ₁), a second capacitor (C2) coupled to a second signal source (φ₂), a drain (24) of a first n-channel field effect transistor (MN1) coupled to the first capacitor (C1), and a source (20) of the first n-channel field effect transistor (MN1) coupled to the first node (11). A source (36) of a first p-channel field effect transistor (MP1) couples to a second node (12) and a gate (34) of the first p-channel field effect transistor (MP1) couples to the second capacitor (C2). The gate (34) and drain (32) of the first p-channel transistor (MP1) couple to the gate (22) and drain (24) of the first n-channel transistor (MN1), respectively. The charge pump (510) comprises a source (26) of a second n-channel field effect transistor (MN2) coupled to the first node (11) and a gate (28) of the second n-channel transistor (MN2) coupled to the first capacitor (C1). A source (42) of a second p-channel field effect transistor (MP2) couples to the second node (12), and a drain (38) of the second p-channel transistor (MP2) is coupled to the second capacitor (C2). The gate (40) and drain (38) of the second p-channel transistor (MP2) couple to the gate (28) and drain (30) of the second n-channel transistor (MN2), respectively.

Claims

1. A charge pump, comprising:

a first capacitor coupled to a first signal source;

a second capacitor coupled to a second signal source;

a first n-channel field effect transistor comprising a first gate, a first drain coupled to the first capacitor, and a first source coupled to a first node;

a first p-channel field effect transistor comprising a second source coupled to a second node, a second gate coupled to the second capacitor and to the first gate, and a second drain coupled to the first drain;

a second n-channel field effect transistor comprising a third drain, a third source coupled to the first node, and a third gate coupled to the first capacitor;

a second p-channel field effect transistor comprising a fourth source coupled to the second node, a fourth drain coupled to the second capacitor and to the third drain, and a fourth gate coupled to the third gate;

a first resistor coupling the source of the first p-channel transistor to the second node; and

a second resistor coupling the source of the second p-channel transistor to the second node.

2. A charge pump, comprising:

a first capacitor coupled to a first signal source;

a second capacitor coupled to a second signal source;

a first n-channel field effect transistor comprising a first gate, a first drain coupled to the first capacitor, and a first source coupled to a first node;

a first p-channel field effect transistor comprising a second source coupled to a second node, a second gate coupled to the second capacitor and to the first gate, and a second drain coupled to the first drain;

a second n-channel field effect transistor comprising a third drain, a third source coupled to the first node, and a third gate coupled to the first capacitor;

a second p-channel field effect transistor comprising a fourth source coupled to the second node, a fourth drain coupled to the second capacitor and to the third drain, and a fourth gate coupled to the third gate;

a first resistor coupling the source of the first p-channel transistor to the second node; and

a second resistor coupling the source of the second p-channel transistor to the second node.

3. The charge pump of claim 2, further comprising:

a first back gate coupled to the source of the first n-channel transistor and to the first node;

a second back gate coupled to the source of the second n-channel transistor and to the first node;

a third back gate coupled to the source of the first p-channel transistor and to the second node; and

a fourth back gate coupled to the source of the second p-channel transistor and to the second node.

4. A charge pump, comprising:

a first capacitor coupled to a first signal source;

a second capacitor coupled to a second signal source;

a first n-channel field effect transistor comprising a first gate, a first drain coupled to the first capacitor, and a first source coupled to a first node;

a first p-channel field effect transistor comprising a second source coupled to a second node, a second gate coupled to the second capacitor and to the first gate, and a second drain coupled to the first drain;

a second n-channel field effect transistor comprising a third drain, a third source coupled to the first node, and a third gate coupled to the first capacitor;

a second p-channel field effect transistor comprising a fourth source coupled to the second node, a fourth drain coupled to the second capacitor and to the third drain, and a fourth gate coupled to the third gate;

a first back gate coupled to the source of the first n-channel transistor and to the first node;

a second back gate coupled to the source of the second n-channel transistor and to the first node;

a third back gate coupled to the source of the first p-channel transistor and to the second node;

a fourth back gate coupled to the source of the second p-channel transistor and to the second node;

a first resistor coupling the source of the first p-channel transistor to the second node; and

a second resistor coupling the source of the second p-channel transistor to the second node.

5. The charge pump of claim 4, wherein the first and second n-channel transistors are isolated from the first and second p-channel transistors using reverse-biased PN-junctions.

6. The charge pump of claim 4, wherein the first and second n-channel transistors are isolated from the first and second p-channel transistors using an insulating dielectric.

7. An integrated circuit comprising:

a first stage charge pump coupled to a first node, the first stage charge pump comprising;

a first capacitor coupled to a first signal source;

a second capacitor coupled to a second signal source;

a first n-channel field effect transistor comprising a first gate, a first drain coupled to the first capacitor, and a first source coupled to the first node;

a first p-channel field effect transistor comprising a second source coupled to a second node, a second gate coupled to the second capacitor and to the first gate, and a second drain coupled to the first drain;

a second n-channel field effect transistor comprising a third drain, a third source coupled to the first node, and a third gate coupled to the first capacitor;

a second p-channel field effect transistor comprising a fourth source coupled to the second node, a fourth drain coupled to the second capacitor and to the third drain, and a fourth gate coupled to the third gate;

load circuitry coupled to the second node of the first stage charge pump;

a first resistor coupling the source of the first p-channel transistor to the load circuitry; and

a second resistor coupling the source of the second p-channel transistor to the load circuitry.

8. The integrated circuit of claim 7, further comprising a second stage charge pump operable to couple the first stage charge pump to the load circuitry.

9. The integrated circuit of claim 8, wherein the second stage charge pump comprises:

a third capacitor coupled to a third signal source;

a fourth capacitor coupled to a fourth signal source;

a third n-channel field effect transistor comprising a fifth gate, a fifth drain coupled to the third capacitor, and a fifth source coupled to the second node;

a third p-channel field effect transistor comprising a sixth source coupled to a third node, the third node coupled to the load circuitry, a sixth gate coupled to the fourth capacitor and to the fifth gate, and a sixth drain coupled to the fifth drain;

a fourth n-channel field effect transistor comprising a seventh drain, a seventh source coupled to the second node, and a seventh gate coupled to the third capacitor; and

a fourth p-channel field effect transistor comprising an eighth source coupled to the third node, an eighth drain coupled to the fourth capacitor and to the seventh drain, and an eighth gate coupled to the seventh gate.

10. The integrated circuit of claim 9, wherein the first and second n-channel transistors and the first and second p-channel transistors each comprise a MOSFET.

11. The integrated circuit of claim 7, wherein the first signal source produces a voltage waveform approximately 180°

out of phase with the second signal source.

12. The integrated circuit of claim 7, further comprising:

a first back gate coupled to the source of the first n-channel transistor and to the first node;

a second back gate coupled to the source of the second n-channel transistor and to the first node;

a third back gate coupled to the source of the first p-channel transistor and to the load circuitry; and

a fourth back gate coupled to the source of the second p-channel transistor and to the load circuitry.

13. The integrated circuit of claim 7, wherein the first and second n-channel transistors are each isolated from the first and second p-channel transistors using reverse-biased PN-junctions.

14. The integrated circuit of claim 7, wherein the first and second n-channel transistors are isolated from the first and second p-channel transistors using an insulating dielectric.

15. An integrated circuit comprising:

a first stage charge pump coupled to a first node, the first stage charge pump comprising;

a first capacitor coupled to a first signal source;

a second capacitor coupled to a second signal source;

a first n-channel field effect transistor comprising a first gate, a first drain coupled to the first capacitor, and a first source coupled to the first node;

a first p-channel field effect transistor comprising a second source coupled to a second node, a second gate coupled to the second capacitor and to the first gate, and a second drain coupled to the first drain;

a second n-channel field effect transistor comprising a third drain, a third source coupled to the first node, and a third gate coupled to the first capacitor;

a second p-channel field effect transistor comprising a fourth source coupled to the second node, a fourth drain coupled to the second capacitor and to the third drain, and a fourth gate coupled to the third gate;

load circuitry coupled to the second node of the first stage charge pump;

a first resistor coupling the source of the first p-channel transistor to the load circuitry; and

a second resistor coupling the source of the second p-channel transistor to the load circuitry.

16. A method for making a charge pump, comprising:

coupling a first capacitor to a first signal source;

coupling a second capacitor to a second signal source;

coupling a source of a first n-channel field effect transistor and a source of a second n-channel field effect transistor to a first node;

coupling a drain of the first n-channel field effect transistor and a gate of the second n-channel field effect transistor to the first capacitor;

coupling a source of a first p-channel field effect transistor and a source of a second p-channel field effect transistor to a second node;

coupling the second capacitor to a gate of the first p-channel field effect transistor and a drain of the second p-channel field effect transistor;

coupling the gate of the first p-channel transistor to the gate of the first n-channel transistor, and the drain of the first p-channel transistor to the drain of the first n-channel transistor; and

coupling the gate of the second p-channel transistor to the gate of the second n-channel transistor, and the drain of the second p-channel transistor to the drain of the second n-channel transistor;

wherein the coupling to a second node comprises;

coupling with a first resistor the second node to a first back gate and the source of the first p-channel transistor; and

coupling with a second resistor the second node to a second back gate and the source of the second p-channel transistor.

17. The method of claim 16, wherein the coupling a first node further comprises:

coupling a first back gate and the source of the first n-channel transistor to the first node; and

coupling a second back gate and the source of the second n-channel transistor to the first node.

18. The method of claim 16, wherein the first and second n-channel transistors and the first and second p-channel transistors each comprise a MOSFET.

19. The method of claim 16, wherein the first and second n-channel transistors are isolated from the first and second p-channel transistors using reverse-biased PN-junctions.

20. The method of claim 16, wherein the first and second n-channel transistors are each isolated from the first and second p-channel transistors using an insulating dielectric.