Graphic processing method and system for displaying a combination of images

• US 6,429,871 B1
• Filed: 08/29/1997
• Issued: 08/06/2002
• Est. Priority Date: 10/06/1986
• Status: Expired due to Fees

• Current Assignee: Hitachi Engineering Co.,Ltd (Hitachi, Ltd.), Hitachi, Ltd.
• Original Assignee: Hitachi Engineering Co.,Ltd (Hitachi, Ltd.), Hitachi, Ltd.
• Inventors: Sato, Jun, Matsuo, Shigeru, Yokota, Yoshikazu, Sone, Takashi, Kikuchi, Masahiko, Katsura, Koyo
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/921,241
• Time in Patent Office: 1,803 Days
• Field of Search: 345/501, 345/502, 345/505, 345/507-509, 345/522, 345/213, 345/521
• US Class Current: 345/501
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 11/203 Drawing of straight lines or curves
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A graphic processing method and system which is capable of displaying a combination of images from, for example, an external source such as TV signals and graphic data generated by a graphic processor, whereby the graphic processor fetches horizontal synchronizing signals and vertical synchronizing signals, via respective terminals, from a source external of the system, and reads out the data from a frame buffer in accordance with the fetched signals to display the data.

Claims

1. A graphic processing system comprising:

a central processing unit;

a graphic processor receiving commands and parameters from said central processing unit and generating display data using said received commands and parameters in accordance with predetermined processing procedures; and

a memory storing said display data generated by said graphic processor,

wherein said graphic processor has a first terminal for inputting a horizontal synchronizing signal from external of said graphic processing system and a second terminal for inputting a vertical synchronizing signal from external of said graphic processing system, said graphic processor fetches said horizontal synchronizing signal from external of said graphic processing system via said first terminal and fetches said vertical synchronizing signal from external of said graphic processing system via said second terminal, reads out said display data stored in the memory based on at least said fetched vertical synchronizing signal, when a display is set to a non-interlace mode, and reads out said display data stored in the memory based on at least said fetched vertical synchronizing signal of a predetermined timing, when the display is set to an interlace mode.

2. A graphic processing system comprising:

a central processing unit;

a plurality of graphic processors receiving commands and parameters from said central processing unit and generating display data using said received commands and parameters in accordance with predetermined processing procedures; and

a plurality of memories provided for respective ones of said plurality of graphic processors to store said display data generated by said plurality of graphic processors,

wherein each graphic processor has a first terminal for inputting a horizontal synchronizing signal from external of said graphic processing system and a second terminal for inputting a vertical synchronizing signal from external of said graphic processing system, said graphic processor fetches said horizontal synchronizing signal from external of said graphic processing system via said first terminal and fetches said vertical synchronizing signal from external of said graphic processing system via said second terminal, reads out said display data stored in a respective one of said plurality of memories based on at least said fetched vertical synchronizing signal, when a display is set to a non-interlace mode, and reads out said display data stored in the respective one of said plurality of memories based on at least said fetched vertical synchronizing signal of a predetermined timing, when the display is set to an interlace mode.