Embedded CAM test structure for fully testing all matchlines

• US 6,430,072 B1
• Filed: 10/01/2001
• Issued: 08/06/2002
• Est. Priority Date: 10/01/2001
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Rowland, Jeremy P., Ouellette, Michael R., Nadkarni, Rahul K., Chadwick, Thomas B.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/682,638
• Time in Patent Office: 309 Days
• Field of Search: 365/49, 365/189.07, 365/230.06, 365/230.02, 365/201
• US Class Current: 365/49.15
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Abstract

A method and structure for content addressable memory structure having a memory array of words, each word having multiple memory bits and a plurality of matchlines. Each of the matchlines is connected to one of the words and a matchline compare circuit is connected to the matchlines and is adapted to test all of the words individually. The matchline compare circuit includes a plurality of comparators equal in number to a number of the words, such that each word is connected to a dedicated comparator to allow each word in the memory array to be individually tested.

Claims

1. A content addressable memory structure comprising:

a memory array of words, each word having multiple memory bits;

a plurality of matchlines, each of said matchlines being connected to one of said words; and

matchline compare circuit connected to said matchlines and being adapted to test all of said words individually, wherein said matchline compare circuit comprises;

first latches connected to said matchlines;

second latches adapted to store compare data; and

comparators connected to said first latches and said second latches and adapted to compare data in said first latches with said second latches.

2. The structure in claim 1, wherein said structure includes an equal number of words and first latches, such that each matchline is connected to a dedicated first latch.

3. The structure in claim 1, further comprising an alternate match compare signal line connected to said comparators, wherein said comparators compare data in said first latches with data on said alternate match compare signal line.

4. The structure in claim 3, further comprising:

multiplexors connected to said alternate match compare signal line, said second latches, and said comparators; and

a control signal line connected to said multiplexors, said control signal line supplying a control signal that selects, as inputs, one of said alternate match compare signal line and said second latches to be output from said multiplexors to said comparators.

5. The structure in claim 4, wherein said structure includes an equal number of said words, said first latches, said second latches, said multiplexors, and said comparators, such that each word is individually tested by said matchline compare circuit.

6. The structure in claim 4, wherein said alternate match compare signal line carries a test data pattern that does not match data in any word in said memory array.

14. The structure in claim 1, wherein said structure includes an equal number of words and first latches, such that each matchline is connected to a dedicated first latch.

15. The structure in claim 1, further comprising an alternate match compare signal line connected to said comparators, wherein said comparators compare data in said first latches with data on said alternate match compare signal line.

16. The structure in claim 15, further comprising:

multiplexors connected to said alternate match compare signal line, said second latches, and said comparators; and

a control signal line connected to said multiplexors, said control signal line supplying a control signal that selects, as inputs, one of said alternate match compare signal line and said second latches to be output from said multiplexors to said comparators.

17. The structure in claim 16, wherein said structure includes an equal number of said words, said first latches, said second latches, said multiplexors, and said comparators, such that each word is individually tested by said BIST circuit.

7. A content addressable memory structure comprising:

a memory array of words, each word having multiple memory bits;

a plurality of matchlines, each of said matchlines being connected to one of said words; and

a matchline compare circuit connected to said matchlines and being adapted to test all of said words individually,

wherein said matchline compare circuit includes a plurality of comparators equal in number to a number of said words, such tat each word is connected to a dedicated comparator to allow each word in said memory array to be individually tested,

wherein said matchline compare circuit comprises;

first latches connected to said matchlines; and

second latches adapted to store compare data, and

wherein said comparators are connected to said first latches and said second latches and are adapted to compare data in said first latches with said second latches.

8. The structure in claim 7, wherein said structure includes an equal number of words and first latches, such that each matchline is connected to a dedicated first latch.

9. The structure in claim 8, further comprising an alternate match compare signal line connected to said comparators, wherein said comparators compare data in said first latches with data on said alternate match compare signal line.

10. The structure in claim 9, further comprising:

multiplexors connected to said alternate match compare signal line, said second latches, and said comparators; and

a control signal line connected to said multiplexors, said control signal line supplying a control signal that selects, as inputs, one of said alternate match compare signal line and said second latches to be output from said multiplexors to said comparators.

11. The structure in claim 10, wherein said structure includes an equal number of said words, said first latches, said second latches, said multiplexors, and said comparators, such that each word is individually tested.

12. The structure in claim 10, wherein said alternate match compare signal line carries a test data pattern that does not match data in any word in said memory array.

13. A content addressable memory structure comprising:

a memory array of words, each word having multiple memory bits;

a plurality of matchlines, each of said matchlines being connected to one of said words; and

a built-in self test (BIST) circuit comprising registers for storing output from said matchlines and comparators for testing data in said registers,

wherein each word is connected to a dedicated comparator to allow each word in said memory array to be individually tested,

wherein said BIST circuit comprises;

first latches connected to said matchlines; and

second latches adapted to store compare data, and

wherein said comparators are connected to said first latches and said second latches and are adapted to compare data in said first latches with said second latches.