Single precision array processor

• US 6,430,589 B1
• Filed: 06/19/1998
• Issued: 08/06/2002
• Est. Priority Date: 06/20/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Jennings, Earle W. III
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/100,448
• Time in Patent Office: 1,509 Days
• Field of Search: 708/620, 708/501, 708/523
• US Class Current: 708/620
• CPC Class Codes: G06F 15/7857 using interleaved memory addressing G06F12/0607
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

A device for performing single precision floating point arithmetic. The device includes a shared operand generator that receives an operand and outputs a result that is a fixed function of the operand. It also includes an arithmetic circuit comprising a plurality of multiply circuits that calculate partial products of a first and second operand and the result of the shared operand generator. It also includes circuitry to calculate the sum of the partial products and a third operand to produce the arithmetic result.

Claims

1. A device comprising:

a shared operand generator, the shared operand generator receiving a first operand and outputting a result that is a fixed function of the first operand; and

an arithmetic circuit comprising;

a plurality of multiply circuits, each of the plurality of multiply circuits having circuitry to calculate partial products of the first operand and a second operand using at least one of a set including the first operand and the result of the shared operand generator, and

circuitry to selectively calculate a sum of the partial products and a third operand and produce an arithmetic result; and

a most significant zero detector for determining the bit position in the arithmetic circuit result of the most significant zero.

2. The device of claim 1 wherein the result of the shared operand generator is stored in a register.

3. The device of claim 2 wherein the first operand is stored in a register.

4. The device of claim 1 wherein the third operand is stored in a register.

5. The device of claim 1 wherein the fixed function is an arithmetic function.

6. The device of claim 1 wherein the fixed function is a multiplication by three.

7. The device of claim 1 wherein the second input of each of the plurality of multiply circuits is coupled to a different operand.

8. The device of claim 1 wherein the second inputs of each of the plurality of multiply circuits are not coupled to the same operand.

9. The device of claim 1 further comprising a plurality of bit multipliers in the arithmetic circuit, wherein each of the plurality of bit multipliers multiplies a different bit of the second operand with the first operand to produce the partial products.

10. The device of claim 9 wherein the second operand comprises a collection of subsets of digits which taken as a whole represent the value of the second operand.

11. The device of claim 10 wherein the second operand comprises subsets comprising 3 distinct digits and one shared digit in each subset.

12. The device of claim 9 further comprising an adder tree for adding the partial products and the third input.

13. The device of claim 1 further comprising an output formatter for formatting the arithmetic circuit result.

14. The device of claim 1 wherein the first and second operands are floating point operands.

15. A device comprising:

a shared operand generator, the shared operand generator receiving a first operand and outputting a result that is a fixed function of the first operand; and

an arithmetic circuit comprising;

a plurality of multiply circuits, each of the plurality of multiply circuits having circuitry to calculate partial products of the first operand and a second operand using at least one of a set including the first operand and the result of the shared operand generator, and

circuitry to selectively calculate a sum of the partial products and a third operand and produce an arithmetic result;

a most significant zero detector for determining the bit position in the arithmetic circuit result of the most significant zero; and

wherein the most significant zero detector further comprises a first stage with a plurality of zero bit detectors each operating on a subset of the sum, a second stage with a plurality of zero bit detectors operating on the results of the first stage, and a third stage with a zero bit detector operating on the results of the second stage.

16. A device for performing multiply/accumulate operations based upon a multiplication algorithm utilizing successive small bit multiply operations, comprising:

a shared operand generator for receiving a first operand and outputting a result that is a fixed function of the first operand; and

an arithmetic circuit comprising;

a plurality of small bit multipliers, wherein each of the plurality of small bit multipliers operates to perform the multiplication algorithm on a first input and a bit of a second input to calculate a plurality of partial products, wherein the first input is one of a set including the first operand and the result of the shared operand generator;

an adder tree for adding the partial products and a third input to calculate a multiply/accumulate result; and

a most significant zero detector for determining the bit position in the arithmetic circuit result of the most significant zero.

17. The device of claim 16 wherein the adder tree comprises a first local carry adder for adding a first subset of the plurality of partial products, a second local carry adder for adding a second subset of the plurality of partial products, and a third local carry adder for adding the results of the first and second local carry adders.

18. The device of claim 17 further comprising a fourth local carry adder for adding a third subset of the plurality of partial products, wherein the third local carry adder adds the results of the first, second, and fourth local carry adders.

19. The device of claim 18 further comprising alignment circuitry for aligning the results of the fourth local carry adder.

20. The device of claim 17 wherein the second carry adder adds the third input with the second subset of the plurality of partial products.

21. The device of claim 17 further comprising alignment circuitry for aligning the results of the third local carry adder.