Method, device and article of manufacture for efficient task scheduling in a multi-tasking preemptive priority-based real-time operating system

• US 6,430,593 B1
• Filed: 03/10/1998
• Issued: 08/06/2002
• Est. Priority Date: 03/10/1998
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lindsley, Brett Louis
• Primary Examiner(s): Courtenay, III, St. John
• Assistant Examiner(s): Nguyen, Van H.
• Application Number:
  US09/037,173
• Time in Patent Office: 1,610 Days
• Field of Search: 709/102, 709/107, 709/108, 709/325, 709/103, 710/19, 710/266, 713/323, 712/228, 712/229, 712/42, 712/43, 712/244, 712/246, 712/34
• US Class Current: 718/103
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

The present invention provides a method, an article of manufacture and a multi-tasking, preemptive, priority based operating device for acceleration of operating system functions using a host processor and a task scheduling accelerator. The host processor processes a plurality of tasks and receives interrupts and uses a predetermined task scheduling accelerator interrupt service routine for responding to the task scheduling accelerator. The task scheduling accelerator is coupled to the host processor and is used for efficiently accelerating real time multi-tasking decisions using scheduling decisions responsive to tasks in the host processor.

Claims

1. A multi-tasking, preemptive, priority based operating device for acceleration of operating system functions comprising:

a host processor, for processing a plurality of tasks, receiving interrupts and using a predetermined task scheduling accelerator interrupt service routine unit for responding to a task scheduling accelerator; and

the task scheduling accelerator, coupled to the host processor, comprising;

an interrupt service routine interface, coupled to the task scheduling accelerator interrupt service routine unit and a state machine of the task scheduling accelerator, for asserting an interrupt and indicating a status of the interrupt;

a semaphore post queue interface, coupled to the task scheduling accelerator interrupt service routine unit and a semaphore post interface, for efficient determination of semaphore index queue status;

a status unit, coupled to the state machine of the task scheduling accelerator and an asynchronous task command interface, for providing a status of an asynchronous task command interface;

the asynchronous task command interface, coupled to the task scheduling accelerator interrupt service routine unit and the semaphore post interface, for receiving commands from the plurality of tasks and device interrupt service routines of the host processor;

a synchronous task command interface, coupled to the task scheduling accelerator interrupt service routine unit, a task scheduling programming interface and to the state machine, for receiving commands from the plurality of tasks of the host processor;

a current execution priority storage unit, coupled to the state machine, for storing a priority of a currently executing task of the plurality of tasks on the host processor;

a plurality of ready task counters, coupled to the state machine, for storing counts of ready tasks of the plurality of tasks at each priority level; and

the state machine, coupled to the interrupt service routine interface, the semaphore post-queue interface, the status unit, the asynchronous task command interface, the synchronous task command interface, the plurality of ready task counters, and the current execution priority storage unit, for determining scheduling decisions.

2. The multi-tasking, preemptive, priority based operating device of claim 1 wherein the asynchronous task command interface comprises a semaphore post count unit, a semaphore post priority unit and a semaphore post index unit, each coupled to the task scheduling accelerator interrupt service routine unit and the semaphore post interface unit, for determining a semaphore post written status and storing a semaphore post count, a semaphore post priority and a semaphore post index.

3. The multi-tasking, preemptive, priority based operating device of claim 1 wherein the synchronous task command interface includes:

a parameter unit, coupled to the task scheduling accelerator interrupt service routine unit, a task scheduling accelerator modify priority unit, a task scheduling accelerator add task unit, and a task scheduling accelerator semaphore pend count unit, for storing a synchronous task command value;

the task scheduling accelerator modify priority unit, coupled to a task scheduling programming interface modify priority unit, for generating a modify priority status and a modify priority command value;

the task scheduling accelerator add task unit, coupled to a task scheduling programming interface add task unit, for generating an add task status and an add task command value;

the task scheduling accelerator semaphore pend count unit, coupled to a task scheduling programming interface semaphore pend unit, for generating a semaphore pend count command value;

a semaphore pend index unit, coupled to the task scheduling accelerator interrupt service routine unit and the task scheduling programming interface semaphore pend unit, for generating a semaphore pend status value and storing a semaphore pend index value;

a task command unit, coupled to the task scheduling accelerator interrupt service routine unit and the state machine, to receive status values from the task scheduling accelerator modify priority unit, the task scheduling accelerator add task unit, and a semaphore pend index unit, and responsive to a task scheduling programming interface task exit unit and a task scheduling programming interface task yield unit for storing status values.

4. The multi-tasking, preemptive, priority based operating device of claim 1 wherein the interrupt service routine interface includes:

an interrupt status information interface, coupled to the task scheduling accelerator interrupt service routine and the state machine, for indicating a status of the interrupt and storing task switch control values; and

an interrupt generator, coupled to the interrupt status information interface, for asserting the interrupt to the host processor.

5. The multi-tasking, preemptive, priority based operating device of claim 1 wherein the host processor comprises:

a semaphore index queue unit, coupled to a semaphore post interface, for storing pending semaphore post requests;

a data structures unit, coupled to a task scheduling accelerator interrupt service routine unit, a semaphore post interface and a task scheduling programming interface, for storing a current state of multiple tasks;

a task unit, for executing predetermined functions on the host processor and generating task scheduling commands;

a device interrupt service routine unit, for implementing predetermined service routines for devices on the host processor and generating task scheduling commands;

the task scheduling accelerator interrupt service routine unit, coupled to an interrupt service routine interface, a semaphore post queue interface, a status unit, the data structures unit and the semaphore index queue unit, for processing interrupt requests from the task scheduling accelerator;

the task scheduling programming interface unit, coupled to the task unit, the data structures unit and a synchronous task command interface, responsive to tasks, for controlling the task scheduling accelerator;

the semaphore post interface, coupled to the data structures unit, the device interrupt service routines unit, the semaphore post queue interface unit, the status unit and the task unit, for controlling the task scheduling accelerator.

6. The multi-tasking, preemptive, priority based operating device of claim 5 wherein the data structures unit stores:

a currently executing task;

lists of tasks ready for execution at each priority level;

lists of tasks pending for semaphores for each semaphore; and

a counter for each semaphore; and

a priority of each task.

7. The multi-tasking, preemptive, priority based operating device of claim 5 wherein the task scheduling programming interface unit responsive to the task unit, provides units for adding a new task, exiting a task, yielding to another task, modifying a priority of a currently executing task and semaphore pend of a semaphore.

8. The multi-tasking, preemptive, priority based operating device of claim 7 wherein the task scheduling programming interface add task unit further initiates by:

adding a new task to the data structure unit;

indicating a new task priority to the task scheduling accelerator add task unit;

comparing the new task priority to a current execution priority; and

asserting the interrupt if the new task priority is higher than the current execution priority.

9. The multi-tasking, preemptive, priority based operating device of claim 8 wherein, when the new task priority is higher than the current execution priority, the task scheduling accelerator interrupt service routine unit initiates modification of the data structures unit in response to the interrupt status information interface to switch to the new added task.

10. The multi-tasking, preemptive, priority based operating device of claim 7 wherein the task scheduling programming interface task exit unit further initiates activity by:

indicating a task exit status to task scheduling accelerator task command unit, determining if a task is ready at the same or lower priority level using the ready task counters unit, and asserting the interrupt.

11. The multi-tasking, preemptive, priority based operating device of claim 10 wherein, when the interrupt status information interface unit indicates a task has been found, the task scheduling accelerator interrupt service routine unit initiates modification of the data structures unit in response to the interrupt status information interface to switch to the found task.

12. The multi-tasking, preemptive, priority based operating device of claim 10 wherein, when the interrupt status information interface unit indicates the task set is idle, the task scheduling accelerator interrupt service routine unit initiates modification of the data structures unit in response to the interrupt status information interface and idles the host processor.

13. The multi-tasking, preemptive, priority based operating device of claim 7 wherein the task scheduling programming interface task yield unit further initiates by:

indicating a task yield status to task scheduling accelerator task command unit, and asserting the interrupt if the ready task counter at the priority specified by the current execution priority unit is non-zero.

14. The multi-tasking, preemptive, priority based operating device of claim 13 when the ready task counter at the current execution priority is non-zero, the task scheduling accelerator interrupt service routine unit initiates modification of the data structures unit in response to the interrupt status information interface to switch to a first task in the task list.

15. The multi-tasking, preemptive, priority based operating device of claim 7 wherein the task scheduling programming interface modify priority unit further initiates by:

indicating a changed priority to the task scheduling accelerator modify priority unit;

asserting the interrupt if there is a higher priority ready task with a priority less than or equal to the current execution priority unit but higher than the changed priority.

16. The multi-tasking, preemptive, priority based operating device of claim 15 when there is a higher priority ready task with a priority less than or equal to the current execution priority unit but higher than the changed priority, the task scheduling accelerator interrupt service routine unit initiates modification of the data structures unit in response to the interrupt status information interface to switch to the higher priority ready task.

17. The multi-tasking, preemptive, priority based operating device of claim 7 wherein the task scheduling programming interface semaphore pend unit further initiates activity in the following units:

decrementing a semaphore count in the data structures unit according to a semaphore index, indicating the decremented semaphore count to the synchronous task command semaphore pend count unit, indicating the semaphore index to the synchronous task command semaphore pend index unit, comparing the semaphore pend count to less than zero, and asserting the interrupt if the semaphore pend count is less than zero.

18. The multi-tasking, preemptive, priority based operating device of claim 17 wherein,when the decremented semaphore count is less than zero, the task scheduling accelerator determines a next ready task at the same or lower priority level.

19. The multi-tasking, preemptive, priority based operating device of claim 18 wherein, when the interrupt status information interface unit indicates a found task, the task scheduling accelerator interrupt service routine unit initiates modification of the data structures unit in response to the interrupt status information interface to switch to the found task.

20. The multi-tasking, preemptive, priority based operating device of claim 18 wherein, when the interrupt status information interface unit indicates the task state is idle, the task scheduling accelerator interrupt service routine unit initiates modification of the data structures unit in response to the interrupt status information interface and idles the host processor.

21. The multi-tasking, preemptive, priority based operating device of claim 5 wherein the semaphore post interface unit further initiates activity in the following units:

incrementing a semaphore count in the data structures unit according to a semaphore index, indicating the incremented semaphore count to semaphore post count unit, indicating the priority of a first task pending on a semaphore to semaphore post priority unit, indicating the semaphore index to semaphore post index unit, comparing the incremented semaphore count to less than or equal to zero, and asserting the interrupt if the incremented semaphore count is less than or equal to zero.

22. The multi-tasking, preemptive, priority based operating device of claim 21 wherein when the incremented semaphore count is less than or equal to zero and the host processor is currently idle, the task scheduling accelerator interrupt service routine unit initiates modification of the data structures unit in response to the interrupt status information interface and activates the first task pending on the semaphore.

23. The multi-tasking, preemptive, priority based operating device of claim 21 wherein when the incremented semaphore count is less than or equal to zero and the priority of the first task pending on the semaphore is less or equal to the current execution priority, the task scheduling accelerator interrupt service routine unit initiates modification of the data structures unit in response to the interrupt status information interface to remove the first task pending on the semaphore in the data structures unit and add it to another list in the data structures unit.

24. The multi-tasking, preemptive, priority based operating device of claim 21 wherein when the incremented semaphore count is less than or equal to zero and the priority of the first task pending on the semaphore is higher than the current execution priority, the task scheduling accelerator interrupt service routine unit initiates modification of the data structures unit in response to the interrupt status information interface to switch to the first task pending on the semaphore.

25. A multi-tasking, preemptive, priority based operating device for acceleration of operating system functions comprising:

a host processor, for processing a plurality of tasks and receiving interrupts, for using a task scheduling accelerator interrupt service routine unit for responding to a task scheduling accelerator; and

the task scheduling accelerator, coupled to the host processor by at least a data bus, an address bus and an interrupt line, for efficiently accelerating real time multitasking decisions using scheduling decisions responsive to tasks in the host processor, the task scheduling accelerator comprising;

an interrupt service routine interface, coupled to the task scheduling accelerator interrupt service routine unit and a state machine of the task scheduling accelerator, for asserting an interrupt and indicating a status of the interrupt;

a semaphore post queue interface, coupled to the task scheduling accelerator interrupt service routine unit and a semaphore post interface, for efficient determination of semaphore index queue status;

a status unit, coupled to the state machine of the task to scheduling accelerator and an asynchronous task command interface, for providing a status of the asynchronous task command interface;

the asynchronous task command interface, coupled to the task scheduling accelerator interrupt service routine unit is and the semaphore post interface, for receiving commands from tasks and device interrupt service routines of the host processor;

a synchronous task command interface, coupled to the task scheduling accelerator interrupt service routine unit, a task scheduling programming interface and to the state machine, for receiving commands from tasks of the host processor;

a current execution priority storage unit, coupled to the state machine, for storing a priority of a currently executing task on the host processor;

a plurality of ready task counters, coupled to the state machine, for storing counts of ready tasks at each priority level; and

the state machine, coupled to the interrupt service routine interface, the semaphore post-queue interface, the status unit, the asynchronous task command interface, the synchronous task command interface, the plurality of ready task counters, and the current execution priority storage unit, for determining scheduling decisions.

26. The multi-tasking, preemptive, priority based operating device of claim 25 wherein the asynchronous task command interface comprises a semaphore post count unit, a semaphore post priority unit and a semaphore post index unit, each coupled to the task scheduling accelerator interrupt service routine unit and the semaphore post interface unit, for determining a semaphore post written status and storing a semaphore post count, a semaphore post priority and a semaphore post index.

27. The multi-tasking, preemptive, priority based operating device of claim 25 wherein the synchronous task command interface includes:

a parameter unit, coupled to the task scheduling accelerator interrupt service routine unit, a task scheduling accelerator modify priority unit, a task scheduling accelerator add task unit, and a task scheduling accelerator semaphore pend count unit, for storing a synchronous task command value;

the task scheduling accelerator modify priority unit, coupled to a task scheduling programming interface modify priority unit, for generating a modify priority status and a modify priority command value;

the task scheduling accelerator add task unit, coupled to a task scheduling programming interface add task unit, for generating an add task status and an add task command value;

the task scheduling accelerator semaphore pend count unit, coupled to a task scheduling programming interface semaphore pend unit, for generating a semaphore pend count command value;

a semaphore pend index unit, coupled to the task scheduling accelerator interrupt service routine unit and the task scheduling programming interface semaphore pend unit, for generating a semaphore pend status value and storing a semaphore pend index value;

a task command unit, coupled to the task scheduling accelerator interrupt service routine unit and the state machine, to receive status values from the task scheduling accelerator modify priority unit, the task scheduling accelerator add task unit, and a semaphore pend index unit; and

responsive to a task scheduling programming interface task exit unit and a task scheduling programming interface task yield unit for storing status values.

28. The multi-tasking, preemptive, priority based operating device of claim 25 wherein the interrupt service routine interface includes:

an interrupt status information interface, coupled to the task scheduling accelerator interrupt service routine and the state machine, for indicating a status of the interrupt and storing task switch control values; and

an interrupt generator, coupled to the interrupt status information interface, for asserting the interrupt to the host processor.

29. The multi-tasking, preemptive, priority based operating device of claim 26 wherein the host processor comprises:

a semaphore index queue unit, coupled to a semaphore post interface for storing pending semaphore post requests;

a data structures unit, coupled to the task scheduling accelerator interrupt service routine unit, the semaphore post interface and a task scheduling programming interface, for storing a current state of multiple tasks;

a task unit, for executing predetermined functions on the host processor and generating task scheduling commands;

a device interrupt service routine unit, for implementing predetermined service routines for devices on the host processor and generating task scheduling commands;

a task scheduling accelerator interrupt service routine unit, coupled to an interrupt service routine interface, a semaphore post queue interface, a status unit, the data structures unit and the semaphore index queue unit, for processing interrupt requests from the task scheduling accelerator;

a device interrupt service routine unit, for implementing predetermined service routines for devices on the host processor;

the task scheduling programming interface unit, coupled to the task unit, the data structures unit and a synchronous task command interface, responsive to tasks, for controlling the task scheduling accelerator; and

the semaphore post interface, coupled to the data structures unit, the device interrupt service routines unit, semaphore post queue interface unit, the status unit and the task unit, for controlling the task scheduling accelerator.

30. The multi-tasking, preemptive, priority based operating device of claim 29 wherein the data structures unit stores:

a currently executing task;

lists of tasks ready for execution at each priority level;

lists of tasks pending for semaphores for each semaphore; and

a counter for each semaphore; and

a priority of each task.

31. The multi-tasking, preemptive, priority based operating device of claim 29 wherein the task scheduling programming interface unit responsive to the task unit, provides units for adding a new task, exiting a task, yielding to another task, modifying a priority of a currently executing task and semaphore pend of a semaphore.

32. A method for implementing a multi-tasking, preemptive, priority based operating device for acceleration of operating system functions comprising the steps of:

processing a plurality of tasks and received interrupts by a host processor using a predetermined task scheduling accelerator interrupt service routine to respond to a task scheduling accelerator; and

accelerating, by a task scheduling accelerator, real time multi-tasking decisions using scheduling decisions responsive to tasks of the plurality of tasks in the host processor, wherein the step of accelerating includes the steps of;

using an interrupt service routine interface for asserting an interrupt and indicating a status of the interrupt;

utilizing a semaphore post queue interface for efficient determination of semaphore index queue status;

using a status unit for providing a status of a asynchronous task command interface;

utilizing the asynchronous task command interface for receiving commands from the tasks and device interrupt service routines of the host processor;

using a synchronous task command interface for receiving commands from the tasks of the host processor;

utilizing a current execution priority storage unit for storing a priority of a currently executing task of the plurality of tasks on the host processor;

using a plurality of ready task counters for storing counts of ready tasks of the plurality of tasks at each priority level; and

utilizing a state machine for determining scheduling decisions.

33. The method of claim 32 wherein utilizing the asynchronous, task command interface includes using a semaphore post count unit, a semaphore post priority unit and a semaphore post index unit for determining a semaphore post written status and storing a semaphore post count, a semaphore post priority and a semaphore post index.

34. The method of claim 32 wherein using the synchronous task command interface includes:

using a parameter unit for storing a synchronous task command value;

using a task scheduling accelerator modify priority unit for generating a modify priority status and a modify priority command value;

using a task scheduling accelerator add task unit for generating an add task status and an add task command value;

using a task scheduling accelerator semaphore pend count unit for generating a semaphore pend count and a semaphore pend count command value;

using a semaphore pend index unit for generating a semaphore pend status value and storing a semaphore pend index value;

using a task command unit to receive status values from the task scheduling accelerator modify priority unit, the task scheduling accelerator add task unit, and a semaphore pend index unit; and

responsive to a task scheduling programming interface task exit unit and a task scheduling programming interface task yield unit for storing status values.

35. The method of claim 32 wherein using the interrupt service routine interface includes:

using an interrupt status information interface for indicating a status of the interrupt and storing task switch control values; and

using an interrupt generator for asserting the interrupt to the host processor.

36. The method of claim 32 wherein using the host processor includes:

using a semaphore index queue unit for storing pending semaphore post requests;

using a data structures unit for storing a current state of multiple tasks;

using a task unit for executing predetermined functions on the host processor and generating task scheduling commands;

using a device interrupt service routine unit for implementing predetermined service routines for devices on the host processor and generating task scheduling commands;

using a task scheduling accelerator interrupt service routine unit for processing interrupt requests from the task scheduling accelerator;

using a task scheduling programming interface unit for controlling the task scheduling accelerator; and

using a semaphore post interface for controlling the task scheduling accelerator.

37. The method of claim 36 wherein using the data structures unit includes storing:

a currently executing task;

lists of tasks ready for execution at each priority level;

lists of tasks pending for semaphores for each semaphore; and

a counter for each semaphore; and

a priority of each task.

38. The method of claim 36 wherein using the task scheduling programming interface unit includes providing units for adding a new task, exiting a task, yielding to another task, modifying a priority of a currently executing task and semaphore pend of a semaphore.

39. An article of manufacture having a multi-tasking, preemptive, priority based operating processing device for acceleration of operating system functions, wherein the device comprises:

a host processor, for processing a plurality of tasks, receiving interrupts and using a task scheduling accelerator interrupt service routine unit for responding to a task scheduling accelerator; and

the task scheduling accelerator, coupled to the host processor, for efficiently accelerating real time multitasking decisions using scheduling decisions responsive to the plurality of tasks in the host processor, the task schedulity accelerator comprising;

an interrupt service routine interface, coupled to the task scheduling accelerator interrupt service routine unit and a state machine of the task scheduling accelerator, for asserting an interrupt and indicating a status of the interrupt;

a semaphore post queue interface, coupled to the task scheduling accelerator interrupt service routine unit and a semaphore post interface, for efficient determination of semaphore index queue status;

a status unit, coupled to the state machine of the task scheduling accelerator and an asynchronous task command interface, for providing a status of the asynchronous task command interface;

the asynchronous task command interface, coupled to the task scheduling accelerator interrupt service routine unit and a semaphore post interface, for receiving commands from tasks and device interrupt service routines of the host processor;

a synchronous task command interface, coupled to the task scheduling accelerator interrupt service routine unit, a task scheduling programming interface and to the state machine, for receiving commands from tasks of the host processor;

a current execution priority storage unit, coupled to the state machine, for storing a priority of a currently executing task on the host processor;

a plurality of ready task counters, coupled to the state machine, for storing counts of ready tasks at each priority level; and

the state machine, coupled to the interrupt service routine interface, the semaphore post-queue interface, the status unit, the asynchronous task command interface, the synchronous task command interface, the plurality of ready task counters, and the current execution priority storage unit, for determining scheduling decisions.

40. The article of manufacture of claim 39 wherein the asynchronous task command interface comprises a semaphore post count unit, a semaphore post priority unit and a semaphore post index unit, each coupled to the task scheduling accelerator interrupt service routine unit and the semaphore post interface unit, for determining a semaphore post written status.

41. The article of manufacture of claim 39 wherein the synchronous task command interface includes:

a parameter unit, coupled to the task scheduling accelerator interrupt service routine unit, a task scheduling accelerator modify priority unit, a task scheduling accelerator add task unit, and a task scheduling accelerator semaphore pend count unit, for storing a synchronous task command value;

the task scheduling accelerator modify priority unit, coupled to a task scheduling programming interface modify priority unit, for generating a modify priority status and a modify priority command value;

the task scheduling accelerator add task unit, coupled to a task scheduling programming interface add task unit, for generating an add task status and an add task command value command value;

the task scheduling accelerator semaphore pend count unit, coupled to a task scheduling programming interface semaphore pend unit, for generating a semaphore pend count;

a semaphore pend index unit, coupled to the task scheduling accelerator interrupt service routine unit and the task scheduling programming interface semaphore pend unit, for generating a semaphore pend status value and storing a semaphore pend index value;

a task command unit, coupled to the task scheduling accelerator interrupt service routine unit and the state machine, to receive status values from the task scheduling accelerator modify priority unit, the task scheduling accelerator add task unit, and a semaphore pend index unit; and

responsive to a task scheduling programming interface task exit unit and a task scheduling programming interface task yield unit for storing status values.

42. The article of manufacture of claim 39 wherein the interrupt service routine interface includes:

an interrupt status information interface, coupled to the task scheduling accelerator interrupt service routine and the state machine, for indicating a status of the interrupt and storing task switch control values; and

an interrupt generator, coupled to the interrupt status information interface, for asserting the interrupt to the host processor.

43. The article of manufacture of claim 39 wherein the host processor comprises:

a semaphore index queue unit, coupled to a semaphore post interface for storing pending semaphore post requests;

a data structures unit, coupled to a task scheduling accelerator interrupt service routine unit, a semaphore post interface and a task scheduling programming interface, for storing a current state of multiple tasks;

a task unit, for executing predetermined functions on the host processor and generating task scheduling commands;

a device interrupt service routine unit, for implementing predetermined service routines for devices on the host processor and generating task scheduling commands;

a task scheduling accelerator interrupt service routine unit, coupled to an interrupt service routine interface, a semaphore post queue interface, a status unit, the data structures unit and the semaphore index queue unit, for processing interrupt requests from the task scheduling accelerator;

the task scheduling programming interface unit, coupled to the task unit, the data structures unit and a synchronous task command interface, responsive to tasks, for controlling the task scheduling accelerator; and

the semaphore post interface, coupled to the data structures unit, the device interrupt service routines unit, semaphore post queue interface unit, the status unit and the task unit, for controlling the task scheduling accelerator.

44. The article of manufacture of claim 43 wherein the data structures unit stores:

a currently executing task;

lists of tasks ready for execution at each priority level;

lists of tasks pending for semaphores for each semaphore; and

a counter for each semaphore; and

a priority of each task.

45. The article of manufacture of claim 43 wherein the task scheduling programming interface unit responsive to the task unit, provides units for adding a new task, exiting a task, yielding to another task, modifying a priority of a currently executing task and semaphore pend of a semaphore.

46. The article of manufacture of claim 39 wherein the article of manufacture is one of:

a base station, a handheld radio, an engine controller, an electrical musical device, a security system, a cordless telephone, a modem, a fax machine, a disk drive, a cellular telephone, an automotive controller, and a motor control.