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Address generation utilizing an adder, a non-sequential counter and a latch

  • US 6,430,671 B1
  • Filed: 02/10/1998
  • Issued: 08/06/2002
  • Est. Priority Date: 02/10/1998
  • Status: Expired due to Term
First Claim
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1. An address generator for a memory device, said address generator comprising:

  • an adder;

    a non-sequential counter outputting, via a multiplexer, non-sequential numerical data over an unobstructed single data path directly to a first input of said adder; and

    an output latch to latch an output of said adder as an address for said memory device.

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