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Processor and method of prefetching data based upon a detected stride

  • US 6,430,680 B1
  • Filed: 03/31/1998
  • Issued: 08/06/2002
  • Est. Priority Date: 03/31/1998
  • Status: Expired due to Fees
First Claim
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1. A method within a data processing system including a processor and a memory for generating a load address, said method comprising:

  • storing at least a portion of a first instruction address of a first load instruction;

    determining a first difference between a first load target address and a second load target address;

    determining a second difference between said second load target address and a third load target address, said third load target address having a second instruction address associated therewith;

    generating a fourth load target address in response to comparing said first and second differences; and

    supplying said fourth load target address to the memory as a memory request address if a program loop is detected by comparison of said second instruction address and said at least said portion of said first instruction address, wherein said memory is an upper level memory and said data processing system further includes a lower level memory, said supplying step comprising transmitting said fourth load target address to said lower level memory only if data associated with said fourth load target address is neither resident in said upper level memory nor a target of an outstanding memory fetch request transmitted to said lower level memory.

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