Network transceiver having circuitry for referencing transmit data to a selected input clock

• US 6,430,695 B1
• Filed: 04/13/1999
• Issued: 08/06/2002
• Est. Priority Date: 04/17/1998
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: He, Qing, Bray, Michael Richard
• Primary Examiner(s): Coulter, Kenneth R.
• Application Number:
  US09/289,951
• Time in Patent Office: 1,211 Days
• Field of Search: 370/503, 375/219, 375/211, 713/400, 713/501
• US Class Current: 713/501
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 25/242 with retiming
• CPC Class Codes: H04L 41/046 comprising network management agents or mobile agents therefor
• CPC Class Codes: H04L 49/3054 Auto-negotiation, e.g. access control between switch gigabit interface connector [GBIC] and link
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]

Abstract

A novel system for selectively referencing transmit data transferred from a repeater to a physical layer transmitter via a Media Independent Interface (MII), to an input clock selected depending on a mode of MII operations. A clock select input determines whether transmit data is referenced to a selected input clock or to a MII transmit clock output. An analog phase-locked loop (APLL) is supplied with the selected input clock to produce a signal for driving a wave shaper that converts the MII transmit data into a required format for 10 Mb/s operations.

Claims

1. A network transceiver for transferring network signals between a repeater and a link partner provided on a network medium, the transceiver comprising:

a physical layer device,

an interface for transferring transmit data from the repeater to the physical layer device,

a first clock input for providing a first reference clock signal,

a second clock input for providing a second reference clock signal, and

a transmit data referencing circuit for selectively applying the first or the second reference clock signal as a timing reference for transfer of the transmit data.

2. The transceiver of claim 1, wherein the interface is a media independent interface (MII) conforming to IEEE Std. 802.3.

3. The transceiver of claim 1, wherein the transmit data referencing circuit is arranged to reference the transmit data to the first reference clock signal when the interface operates at a first data rate.

4. The transceiver of claim 3, wherein the transmit data referencing circuit is arranged to reference the transmit data to the second reference clock signal when the interface operates at a second data rate.

5. The transceiver of claim 1, wherein the interface is arranged for transferring a transmit clock output signal to the repeater.

6. The transceiver of claim 5, further comprising a clock select input for enabling a user to employ the transmit clock output signal to provide a timing reference for transfer of the transmit data when the clock select input is in a first state, and for selectively referencing the transmit data to the first or the second reference clock signal when the clock select input is in a second state.

7. The transceiver of claim 1, wherein the transmit data referencing circuit comprises a phase-locked loop for producing an internal clock signal at a fixed preset frequency in response to the first or the second reference clock signal.

8. The transceiver of claim 7, wherein the physical layer device comprises a wave shaper for transforming the transmit data into a format appropriate for the link partner.

9. The transceiver of claim 8, wherein the wave shaper is driven by the internal clock signal produced by the phased-locked loop.

10. The transceiver of claim 9, wherein the phase-locked loop comprises a phase detector having a first input for receiving the first or the second reference clock signal.

11. The transceiver of claim 10, wherein the phase-locked loop further comprises a frequency divider coupled between a voltage-controlled oscillator and a second input of the phase detector.

12. The transceiver of claim 11, wherein the frequency divider is arranged to divide a frequency of the voltage-controlled oscillator by a first factor when the first reference clock signal is supplied to the phase detector.

13. The transceiver of claim 12, wherein the frequency divider is arranged to divide the frequency of the voltage-controlled oscillator by a second factor when the second reference clock signal is supplied to the phase detector.

14. The transceiver of claim 13, wherein the first and the second factors are selected to maintain the fixed preset frequency at the output of the voltage-controlled oscillator when the first or the second reference clock signal is supplied to the phase detector.

15. In an Ethernet network, a method of transferring network data between a repeater and a link partner provided on a network medium, comprising the steps of:

arranging a media independent interface (MII) for transferring transmit data from the repeater to a physical layer device,

supplying the physical layer device with first and second input clock signals for respectively providing first and second reference clock signals, and

selectively applying the first or the second reference clock signal as a timing reference for transfer of the transmit data.

16. The method of claim 15, wherein the transmit data is referenced to the first reference clock signal when the MII operates at a first data rate, and to the second reference clock signal when the MII operates at a second data rate.

17. The method of claim 15, wherein a transmit clock output signal is transferred to the repeater.

18. The method of claim 17, further comprising the step of supplying the physical layer device with a clock select input signal for enabling a user to employ the transmit clock output signal to provide a timing reference for transfer of the transmit data when the clock select input is in a first state, and for selectively referencing the transmit data to the first or the second reference clock signal when the clock select input is in a second state.

19. The method of claim 15, further comprising the step of transforming the transmit data into a format appropriate for the link partner.

20. The method of claim 19, wherein the step of transforming is controlled by an internal clock signal produced at a fixed preset frequency in response to the first or the second reference clock signal.