Trench DMOS transistor structure having a low resistance path to a drain contact located on an upper surface

• US 6,432,775 B2
• Filed: 06/01/2001
• Issued: 08/13/2002
• Est. Priority Date: 03/01/1999
• Status: Expired due to Term

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): LEE, HSIEN MING
• Application Number:
  US09/873,984
• Publication Number:
  US 20010028085A1
• Time in Patent Office: 438 Days
• Field of Search: 438/268, 438/269, 438/270, 438/272, 438/273, 438/274, 257/330, 257/336
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is also formed within the first region, which also has sides and a bottom. A second region of semiconductor material is located within the first region and adjacent to and near the bottom of the gate trench. The second region extends to a location adjacent to and near the bottom of the drain access trench. The second region is of the first conductivity type and has a higher dopant concentration than the first region. A gate electrode is formed within the gate trench. A layer of gate dielectric material insulates the gate electrode from the first and second regions. A drain region of semiconductor material is located within the drain access trench. The drain region is of a first conductivity type and has a higher dopant concentration than the first region. A source region is formed on the surface of the first semiconductor region and a body region is formed within the first region beneath the source region. The body region has a second conductivity type opposite to the first conductivity type.

Claims

1. A method for forming a semiconductor device comprising the steps of:

providing an article that includes a first region of semiconductor material, doped to a first concentration with a dopant of a first conductivity type, and serving as a drain region;

etching a gate trench within said first region, said gate trench having sides and a bottom;

etching a drain access trench within said first region, said drain access trench having sides and a bottom;

forming a source region on the surface of said first region;

forming a body region within said first region beneath said source region, said body region having a second conductivity type opposite said first conductivity type;

depositing a dielectric material that lines said gate trench;

forming a second region of semiconductor material within said first region, said second region being located adjacent to said gate trench near said bottom of said gate trench and extending adjacent to said drain access trench near said bottom of said drain access trench, said second region being of said first conductivity type and having a higher dopant concentration than said first region;

depositing a gate electrode within said gate trench; and

depositing a semiconductor material within said drain access trench, said semiconductor material filling said drain access trench being of said first conductivity type and having a higher dopant concentration than said first region.

2. The method of claim 1 wherein the step of forming the second region of semiconductor material includes the step of diffusing a dopant material of the first conductivity type through the gate trench and the drain access trench.

3. The method of claim 1 wherein the diffusion step is sufficient to ensure an overlap of material that diffuses through the gate trench and the drain access trench so that a continuous path of the first conductivity type is formed.

4. The method of claim 1 wherein said gate electrode is formed of conductive material.

5. The method of claim 4 wherein said conductive material is selected from the group of materials consisting of aluminum, alloys of aluminum, polycrystalline silicon, refractory metals, and combinations of polycrystalline silicon and refractory metals.

6. The method of claim 1 wherein said gate dielectric material is located along said sides and bottom of said gate trench.

7. The method of claim 1 wherein said article includes a semiconductor substrate upon which said first region is located.

8. The method of claim 7 wherein said semiconductor substrate is doped to said first conductivity type.

9. The method of claim 1 wherein said second region is formed beneath said gate trench and said drain access trench and extends above the bottom of said trenches.

10. The method of claim 1 wherein the drain access trench is greater in width than said gate trench.