8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate

• US 6,432,782 B1
• Filed: 02/02/2001
• Issued: 08/13/2002
• Est. Priority Date: 08/27/1999
• Status: Expired due to Term

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsing Lan, Lu, Tao Cheng, Wang, Mam Tsung
• Primary Examiner(s): Weiss, Howard
• Assistant Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US09/776,290
• Time in Patent Office: 557 Days
• Field of Search: 257/314-326, 438/257-267, 438/300, 438/526
• US Class Current: 438/300
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present application discloses a non-volatile semiconductor memory device for storing up to eight-bits of information. The device has a semiconductor substrate of one conductivity type, a central bottom diffusion region on top of a portion of the semiconductor substrate, a second semiconductor layer on top of the bottom diffusion region, and left and right diffusion regions formed in the second semiconductor layer apart from the central bottom diffusion region thus forming a first vertical channel between the right and central bottom diffusion regions. The device further includes a trapping dielectric layer formed over exposed portions of the semiconductor substrate, left, central and right bottom diffusion regions and second semiconductor layer and a wordline formed over the trapping dielectric layer. A methods of fabricating this novel cell using trench technology is also disclosed.

Claims

1. A method of fabricating a non-volatile semiconductor memory device for storing up to eight-bits of information comprising:

forming a semiconductor substrate of one conductivity type;

implanting ions in the semiconductor substrate to form a bottom diffusion region of a conductive type opposite to the conductivity type of the semiconductor substrate;

growing a second semiconductor layer on at least a portion of said bottom diffusion region;

implanting ions in the second semiconductor layer to form in the second semiconductor layer right and left diffusion regions, said right diffusion region being spaced apart from said left diffusion region to form a first horizontal channel region and from said bottom diffusion region to form a first vertical channel region, said left diffusion region being spaced from said bottom diffusion region to form a second vertical channel region, each of the right and left diffusion regions being of the of the same conductivity type as the bottom diffusion;

trenching the second semiconductor layer outside the first horizontal channel region, the first vertical channel region and the second vertical channel region to form a middle free-standing cell on the semiconductor substrate;

depositing a trapping dielectric structure on exposed faces of the middle free-standing cell and semiconductor substrate; and

depositing a polysilicon control gate on top of the trapping dielectric structure.

2. The method according to claim 1 further comprising forming a left free-standing cell substantially identical to the middle free-standing cell on the semiconductor substrate to the left of the middle free-standing cell, but the left free-standing cell bottom diffusion region being spaced apart from the middle free-standing cell bottom diffusion region to form a second horizontal channel region within the semiconductor substrate in the trench between the left and middle free-standing cells.

3. The method according to claim 2 further comprising forming a right free-standing cell substantially identical to the middle free-standing cell on the semiconductor substrate to the right of the middle free-standing cell, but the right free-standing cell bottom diffusion region being spaced apart from the middle free-standing cell bottom diffusion region to form a third horizontal channel region within the semiconductor substrate in the trench between the right and middle free-standing cells.

4. The method according to claim 3 further comprising making at least one of the first horizontal channel region, the second horizontal channel region, the third horizontal channel region, the first vertical channel region, the second vertical channel, region long enough such that two bits of information can be reliably stored within those long enough channel.

5. The method according to claim 3 further comprising making at least one of the first horizontal channel region, the first vertical channel region and the second vertical channel region long enough such that two bits of information can be reliably stored within those long enough channel.

6. The method according to claim 2 further comprising making at least one of the first horizontal channel region, the second horizontal channel region, the first vertical channel region and the second vertical channel region long enough such that two bits of information can be reliably stored within those long enough channel.