Method of copper electroplating

• US 6,432,821 B1
• Filed: 12/18/2000
• Issued: 08/13/2002
• Est. Priority Date: 12/18/2000
• Status: Expired due to Term

• Current Assignee: Sony Corporation Of America (Sony Group Corp.)
• Original Assignee: Intel Corporation
• Inventors: Collazo-Davila, Christopher, Jentz, Dave W., Dubin, Valery M.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/739,930
• Publication Number:
  US 20020074234A1
• Time in Patent Office: 603 Days
• Field of Search: 438/678, 438/679, 438/687
• US Class Current: 438/678
• CPC Class Codes: C25D 5/18 Electroplating using modulated, pulsed or reversing current
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

An electroplating process for filling damascene structures on substrates, such as wafers having partially fabricated integrated circuits thereon, includes immersing a substrate, under bias, into a copper plating solution to eliminate thin seed layer dissolution and reduce copper oxide, an initiation step to repair discontinuities in a copper seed layer, superfill plating to fill the smallest features, reverse plating to remove the adsorbed plating additives and their by-products from the substrate, a second superfill plating to fill intermediate size features, a second reverse plating to remove adsorbed plating additives and their by-products from the substrate, and a bulk fill plating with high current density to fill large features. The superfill and reverse plating operations may be repeated more than twice prior to bulk filling in order to provide the desired surface morphology.

Claims

1. A method of forming copper interconnect, comprising:

forming trenches in a dielectric layer disposed on a wafer;

forming a barrier layer over the trenches and dielectric layer immersing the wafer, under bias, in a plating solution;

performing a first plating operation at a forward current density between 10 and 30 mA/cm² and for a duration between 2 and 60 seconds;

performing a second plating operation at a reverse current density between 15 and 60 mA/cm²; and

performing a bulk fill plating operation at a forward current density between 30 and 80 mA/cm².

2. The method of claim 1, wherein the first plating operation comprises a first sub-step at a first current density and a second sub-step at a second current density;

wherein the second current density is greater than the first current density.

3. The method of claim 1, further comprising maintaining a period without applying voltage to the wafer between the first plating operation and the second plating operation.

4. The method of claim 1, further comprising performing a third plating operation at a forward current density between 15 and 60 mA/cm²;

and a fourth plating operation at a reverse current density between 15 and 60 mA/cm².

5. The method of claim 4, wherein the first plating operation comprises a first sub-step at a first current density and a second sub-step at a second current density;

wherein the second current density is greater than the first current density.

6. The method of claim 5, further comprising maintaining a period without applying voltage to the wafer between the first plating operation and the second plating operation.

7. The method of claim 1, wherein performing the first plating operation, the second plating operation and the bulk fill operation, each comprise forcing a current in the plating solution between the wafer and at least one electrode disposed in the plating solution.

8. The method of claim 7, wherein subsequent to the first plating operation and the second plating operation, and prior to the second plating operation, forcing of currents is stopped for a predetermined length of time.

9. The method of claim 8, wherein the predetermined length of time is approximately one second.

10. A method of electroplating copper, comprising:

immersing a wafer into a plating bath having a electrode therein;

applying a first voltage between the electrode and the wafer to produce a first forward current;

applying a second voltage between the electrode and the wafer to produce a second forward current;

applying a third voltage between the electrode and the wafer to produce a third forward current;

applying a fourth voltage between the electrode and the wafer to produce a first reverse current;

applying a fifth voltage between the electrode and the wafer to produce a fourth forward current;

applying a sixth voltage between the electrode and the wafer to produce a second reverse current; and

applying a seventh voltage between the electrode and the wafer to produce a fifth forward current.

11. The method of claim 10, wherein the second voltage is greater than the first voltage, and the third voltage is greater than the second voltage.

12. The method of claim 11, wherein the fifth voltage is greater than the third voltage, and the seventh voltage is greater than the fifth voltage.

13. The method of claim 10, wherein the fourth and sixth voltages are nominally the same voltage.

14. The method of claim 12, further comprising, subsequent to applying the third voltage, removing the voltage between the electrode and the wafer.

15. The method of claim 12, further comprising, subsequent to applying the fourth voltage, removing the voltage between the electrode and the wafer.

16. The method of claim 12, further comprising:

subsequent to applying the third voltage and prior to applying the fourth voltage, removing the voltage between the electrode and the wafer;

subsequent to applying the fourth voltage and prior to applying the fifth voltage, removing the voltage between the electrode and the wafer;

subsequent to applying the fifth voltage and prior to applying the sixth voltage, removing the voltage between the electrode and the wafer; and

subsequent to applying the sixth voltage and prior to applying the seventh voltage, removing the voltage between the electrode and the wafer.

17. The method of claim 16, wherein the first, second, third, and fourth forward currents have a current density of between 10 and 30 mA/cm².

18. The method of claim 17, wherein the first and second reverse currents have a current density of between 15 and 60 mA/cm².

19. The method of claim 17, wherein a final forward current has a current density of between 30 and 80 mA/cm².

20. The method of claim 19, wherein the final forward current results from applying the seventh voltage.

21. A method of electroplating a metal layer over a seed layer on a wafer, comprising:

placing the wafer in a plating solution having at least one electrode disposed therein;

performing a plurality of low current plating and low current de-plating operations, followed by a higher current bulk fill operation;

wherein the low current plating operations comprise forcing a forward current density of between 10 and 30 mA/cm², the low current de-plating operations comprise forcing a reverse current density of between 15 and 60 mA/cm², and the bulk fill operation comprises forcing a forward current density of between 30 and 80 mA/cm².

22. The method of claim 21, wherein the metal comprises Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe and CW.

23. The method of claim 22, wherein the low current plating operations have a duration of between 2 and 60 seconds.

24. The method of claim 23, further comprising forcing zero current between the wafer and the electrode subsequent to a low current plating operation and prior to a low current de-plating operation.

25. The method of claim 24, wherein forcing zero current comprises forcing zero current for approximately 1 second.

26. The method of claim 22, wherein a first one of the plurality of low current plating operations includes three sub-steps with each sub-step characterized by forcing a different current density.

27. The method of claim 26, wherein the different current densities are monotonically increasing.

28. The method of claim 27, wherein the first of the three sub-steps repairs a seed layer.

29. The method of claim 28, wherein the second and third of the three sub-steps fill at least one opening in the wafer, the opening having a lateral width of less than 0.3 microns.

30. The method of claim 24, wherein the low current de-plating operations remove at least one adsorbed chemical from the surface of the wafer.

31. The method of claim 30, wherein the at least one adsorbed chemical is mercaptopropansulfonate.