Method of improving electromigration resistance of capped Cu

• US 6,432,822 B1
• Filed: 05/02/2001
• Issued: 08/13/2002
• Est. Priority Date: 05/02/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ngo, Minh Van, Marathe, Amit P., Avanzino, Steven C.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/846,611
• Time in Patent Office: 468 Days
• Field of Search: 438/687, 438/627, 438/628, 438/629, 438/643, 438/644, 438/653, 438/654, 438/678
• US Class Current: 438/687
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material

Abstract

The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by treating the exposed planarized surface of the Cu or Cu alloy with a plasma containing NH₃ and N₂ under mild steady state conditions, thereby avoiding sensitizing the Cu or Cu alloy surface before capping layer deposition with an attendant improvement in electromigration resistance and wafer-to-wafer uniformity. Embodiments include treating the Cu or Cu alloy surface with a plasma at a relatively high N₂ flow rate of about 8,000 to about 9,200 sccm and a relatively low NH₃ flow rate of about 210 to about 310 sccm.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

treating a surface of copper (Cu) or Cu alloy layer with a plasma containing nitrogen (N₂) and ammonia (NH₃) in a chamber to reduce copper oxide on the surface at;

an NH₃ flow rate of about 210 to about 310 sccm; and

a N₂ flow rate of about 8,000 to about 9,200 sccm; and

forming a capping layer on the treated surface of the Cu or Cu alloy layer.

2. The method according to claim 1, introducing silane into the chamber after treating the surface of the Cu or Cu alloy layer with the plasma to form a silicon nitride capping layer.

3. The method according to claim 2, comprising treating the surface of the Cu or Cu alloy layer with the plasma at:

an RF power of about 50 to about 200 watts;

a temperature of about 300°

C. to about 400°

C.; and

a pressure of about 3 Torr. to about 5.0 Torr.

4. The method according to claim 3, comprising treating the surface of the Cu or Cu alloy layer with the plasma for about 5 to about 25 seconds before introducing silane.

5. The method according to claim 2, comprising introducing a wafer containing the Cu or Cu alloy layer into the chamber, wherein the Cu or Cu alloy layer fills an opening in a dielectric layer.

6. The method according to claim 5, comprising:

introducing N₂ into the chamber;

introducing NH₃ into the chamber;

elevating the pressure; and

initiating a plasma after about 10 to about 15 seconds.

7. The method according to claim 2, wherein the Cu or Cu alloy layer constitutes a dual damascene structure comprising a Cu or Cu alloy line in contact with an underlying Cu or Cu alloy via formed in a dielectric layer.

8. The method according to claim 7, wherein the dielectric layer comprises a dielectric material having a dielectric constant (k) less than about 3.9.

9. A method of manufacturing a semiconductor device, the method comprising:

introducing a wafer containing inlaid copper (Cu) or a Cu alloy into a chamber;

treating an exposed surface of the Cu or Cu alloy with a plasma containing ammonia (NH₃) and nitrogen (N₂) at;

an NH₃ flow rate of about 210 to about 310 sccm;

a N₂ flow rate of about 8,000 to about 9,200 sccm;

an RF power of about 50 to about 200 watts;

a temperature of about 300°

C. to about 400°

C.; and

a pressure of about 3 to about 5 Torr;

introducing silane (SiH₄) into the chamber after treating the surface of the Cu or Cu alloy with the plasma; and

depositing a silicon nitride capping layer on the plasma treated Cu or Cu alloy surface.

10. The method according to claim 9, wherein the inlaid Cu or Cu alloy constitutes a dual damascene structure comprising a Cu or Cu alloy line in contact with an underlying Cu or Cu alloy via formed in a dielectric layer and in electrical contact with an underlying metal feature.

11. The method according to claim 10, wherein the dielectric layer comprises a dielectric material having a dielectric constant (k) less than about 3.9.