Methodology of removing misplaced encapsulant for attachment of heat sinks in a chip on board package

• US 6,432,840 B1
• Filed: 06/28/2000
• Issued: 08/13/2002
• Est. Priority Date: 09/03/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hembree, David R.
• Primary Examiner(s): Sherry, Michael J.
• Assistant Examiner(s): PERT, EVAN T
• Application Number:
  US09/606,969
• Time in Patent Office: 776 Days
• Field of Search: 438/106, 438/127, 438/122, 438/118, 438/759
• US Class Current: 438/759
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85002 being a removable or sacrificial coating
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A process for forming a thermally enhanced Chip On Board semiconductor device (10) with a heat sink (30) is described. In one aspect, a thermally conducting filled gel elastomer material (50) or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface (18) to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material (38) which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conducting filled gel elastomer material (70) is applied between a die surface and the inside attachment surface (46) of a cap-style heat sink to eliminate overpressure on the die/substrate interface.

Claims

1. A method for preventing an encapsulant material from adhering to a surface of a semiconductor die, comprising:

applying a layer of material as a mask to a portion of said surface of said semiconductor die, said layer including one of a gel and an elastomeric material;

applying an encapsulant material to a remaining portion of said surface of said semiconductor die;

curing said encapsulant material; and

removing said layer of material from said surface of said semiconductor die.

2. The method of claim 1, wherein said layer of material includes a silicon gel material.

3. The method of claim 1, wherein said layer of material includes a silicon elastomeric material.

4. The method of claim 1, wherein said layer of material includes a material selected from the group of natural rubber, synthetic rubber, and room temperature cured silicon rubber.

5. The method of claim 2, wherein said silicon gel material includes a cross-linked silicon gel material.

6. The method of claim 5, wherein said silicon gel material includes a cross-linked silicon gel material having at least one thermally conductive filler material therein.

7. The method of claim 6, wherein said silicon gel material includes a cross-linked silicon gel material having a plurality of thermally conductive filler materials therein.

8. The method of claim 1, wherein said semiconductor die is bonded to a substrate in a Chip On Board configuration.

9. The method of claim 1, further comprising the steps:

providing a heat sink having at least one surface; and

securing a heat sink to said surface of said semiconductor die.

10. The method of claim 2, wherein said silicon gel material includes a gel elastomer material filled with heat conductive particles whereby heat conductivity is enhanced.

11. The method of claim 10, wherein said heat conductive particles include metal particles, carbon particles, and diamond filled thermally conductive material in particle form.

12. The method of claim 1, wherein said layer of material includes a dam extending a portion of a length of at least one side of said semiconductor die.

13. The method of claim 12, wherein said layer of material includes a dam extending a portion of a length of a plurality of sides of said semiconductor die.

14. The method of claim 9, wherein the heat sink is resiliently mounted to said surface of said semiconductor die.

15. A method for preventing an encapsulant material from adhering to a surface of a chip scale semiconductor package, comprising:

applying a layer of material as a mask to a portion of said surface of said chip scale semiconductor package, said layer including one of a gel and an elastomeric material;

applying an encapsulant material to a remaining portion of said surface of said chip scale semiconductor package;

curing said encapsulant material; and

removing said layer of material from said surface of said chip scale semiconductor package.

16. The method of claim 15, wherein said layer of material includes a silicon gel material.

17. The method of claim 15, wherein said layer of material includes a silicon elastomeric material.

18. The method of claim 15, wherein said layer of material includes a material selected from the group of natural rubber, synthetic rubber, and room temperature cured silicon rubber.

19. The method of claim 16, wherein said silicon gel material includes a cross-linked silicon gel material.

20. The method of claim 19, wherein said silicon gel material includes a cross-linked silicon gel material having at least one thermally conductive filler material therein.

21. The method of claim 20, wherein said silicon gel material includes a cross-linked silicon gel material having a plurality of thermally conductive filler materials therein.

22. The method of claim 15, wherein said chip scale semiconductor package is bonded to a substrate in a Chip On Board configuration.

23. The method of claim 22, further comprising the steps:

providing a heat sink having at least one surface; and

securing a heat sink to said surface of said chip scale semiconductor package.

24. The method of claim 16, wherein said silicon gel material includes a gel elastomer material filled with heat conductive particles whereby heat conductivity is enhanced.

25. The method of claim 24, wherein said heat conductive particles include metal particles, carbon particles, and diamond filled thermally conductive material in particle form.

26. The method of claim 15, wherein said layer of material includes a dam extending a portion of a length of at least one side of said chip scale semiconductor package.

27. The method of claim 26, wherein said layer of material includes a dam extending a portion of a length of a plurality of sides of said chip scale semiconductor package.

28. A method for preventing glob top material from adhering to a surface of a semiconductor die, comprising:

applying a first layer of material to said surface of said semiconductor die, said layer including one of a gel and an elastomeric material;

applying a second layer of material as a mask to a portion of a surface of said first layer of material;

applying an encapsulant material to a remaining portion of said surface of said semiconductor die;

curing said encapsulant material; and

removing said first layer of material from said surface of said semiconductor die.

29. The method of claim 28, wherein said first layer of material and said second layer of material include a silicon gel material.

30. The method of claim 28, wherein said first layer of material and said second layer of material include a silicon elastomeric material.

31. The method of claim 28, wherein said second layer of material includes a material selected from the group of natural rubber, synthetic rubber, and room temperature cured silicon rubber.

32. The method of claim 29, wherein said silicon gel material includes a cross-linked silicon gel material.

33. The method of claim 32, wherein said silicon gel material includes a cross-linked silicon gel material having at least one thermally conductive filler material therein.

34. The method of claim 33, wherein said silicon gel material includes a cross-linked silicon gel material having a plurality of thermally conductive filler materials therein.

35. The method of claim 28, wherein said semiconductor die is bonded to a substrate in a Chip On Board configuration.

36. The method of claim 28, further comprising the steps:

providing a heat sink having at least one surface; and

securing a heat sink to said surface of said second layer of material.

37. The method of claim 29, wherein said silicon gel material includes a gel elastomer material filled with heat conductive particles whereby heat conductivity is enhanced.

38. The method of claim 37, wherein said heat conductive particles include metal particles, carbon particles, and diamond filled thermally conductive material in particle form.

39. The method of claim 28, wherein said second layer of material includes a dam extending a portion of a length of at least one side of said semiconductor die.

40. The method of claim 39, wherein said second layer of material includes a dam extending a portion of a length of a plurality of sides of said semiconductor die.

41. A method for preventing glob top material from adhering to a surface of a semiconductor die, comprising:

applying a layer of material as a mask to a portion of said surface of said semiconductor die;

applying glob top material to a remaining portion of said surface of said semiconductor die;

curing said glob top material; and

removing said layer of material from said surface of said semiconductor die.

42. The method of claim 41, wherein said layer of material includes a silicon gel material.

43. The method of claim 41, wherein said layer of material includes an elastomeric material.

44. The method of claim 41, wherein said layer of material includes a material selected from the group of natural rubber, synthetic rubber, and room temperature cured silicon rubber.

45. The method of claim 42, wherein said silicon gel material includes a cross-linked silicon gel material.

46. The method of claim 45, wherein said silicon gel material includes a cross-linked silicon gel material having at least one thermally conductive filler material therein.

47. The method of claim 46, wherein said silicon gel material includes a cross-linked silicon gel material having a plurality of thermally conductive filler materials therein.

48. The method of claim 41, wherein said semiconductor die is bonded to a substrate in a Chip On Board configuration.

49. The method of claim 41, further comprising the steps:

providing a heat sink having at least one surface; and

securing a heat sink to said surface of said semiconductor die.

50. The method of claim 42, wherein said silicon gel material includes a gel elastomer material filled with heat conductive particles whereby heat conductivity is enhanced.

51. The method of claim 50, wherein said heat conductive particles include metal particles.

52. The method of claim 41, wherein said layer of material includes a dam extending a portion of a length of one side of said semiconductor die.

53. The method of claim 52, wherein said layer of material includes a dam extending a portion of a length of a plurality of sides of said semiconductor die.

54. A method for fabricating a Chip On Board semiconductor device with a heat sink, said method comprising:

providing a semiconductor die having a first side, a second side, and edges therebetween;

providing a substrate;

providing a thermally conductive heat sink member;

attaching the first side of said semiconductor die to said substrate;

covering at least a portion of the second side of said semiconductor die with a material having an exposed surface;

applying a material to encapsulate said edges of said semiconductor die edges;

maintaining said exposed surface of said material covering the second side of said semiconductor die substantially unencapsulated;

curing said material to encapsulate said edges of said semiconductor die;

removing said material having an exposed surface covering the second side of said semiconductor die; and

attaching said heat sink member to the second side of said semiconductor die.

55. The method of claim 54, wherein providing a semiconductor die includes providing a semiconductor die having wire bond pads;

and

wirebonding said wire bond pads of said semiconductor die to said substrate.

56. The method of claim 55, wherein said heat sink member is attached to said semiconductor die between said wire bond pads of said semiconductor die.

57. The method of claim 54, wherein providing a semiconductor die includes providing a semiconductor die having a surface having a grid of circuit connections configured for downbonding to a substrate;

and

attaching said semiconductor die to said substrate includes attaching said grid of circuit connections to said substrate.

58. The method of claim 57, wherein said heat sink member is attached to the non-active back side surface of said semiconductor die.

59. The method of claim 54, wherein said substrate is a printed circuit board.

60. The method of claim 54, wherein the covering the second side of said semiconductor die comprises includes covering the second side of said semiconductor die with a thermally conductive gel elastomer filled with thermally conductive particles.

61. The method of claim 60, wherein said thermally conductive gel elastomer comprises cross-linked silicone.

62. The method of claim 60, wherein said thermally conductive gel elastomer is filled with metal particles.

63. The method of claim 54, wherein attaching said heat sink includes attaching said heat sink member to the second side of said semiconductor die with a thermally conductive adhesive.

64. The method of claim 54, wherein attaching said heat sink includes attaching said heat sink member to the second side said semiconductor die with a polymeric tape.

65. A method for preventing glob top material from adhering to a surface of a semiconductor die, comprising:

applying a layer of gel elastomer material as a mask to a portion of said surface of said semiconductor die;

applying glob top material to the remaining portion said surface of said semiconductor die;

curing said glob top material; and

peeling said gel elastomer material from said surface of said semiconductor die.

66. The method of claim 65, wherein said semiconductor die is attached to a substrate in a Chip On Board configuration.

67. The method of claim 65, further comprising the step of:

attaching a surface of a heat sink to said surface of said semiconductor die.

68. The method of claim 67, wherein said gel elastomer material includes a gel elastomer material filled with particles.

69. A method for fabricating a Chip On Board semiconductor device with a heat sink, said method comprising:

providing a semiconductor die having a first side, a second side, edges therebetween, and electrical terminals;

providing a substrate having electrical connections;

providing a thermally conductive heat sink member;

attaching the first side of said semiconductor die to said substrate;

connecting said electrical terminals of said semiconductor die to said electrical connections of said substrate;

covering at least a portion of the second side of said semiconductor die with a compliant protective layer having an exposed surface;

applying a material to encapsulate said electrical terminals and die edges;

maintaining said exposed surface of said protective layer substantially unencapsulated by said material;

curing said material;

removing said protective layer; and

attaching said heat sink member to the second side of said semiconductor die.

70. The method of claim 69, wherein said step of providing a semiconductor die includes providing a semiconductor die having wire bond pads:

and

connecting said electrical terminals of said semiconductor die includes wirebonding said electrical terminals of said semiconductor die to said connections of said substrate.

71. The method of claim 70, wherein said heat sink member is attached to the second surface of said semiconductor die between said terminals of said semiconductor die.

72. The method of claim 69, wherein providing a semiconductor die includes providing said semiconductor die having an active surface with a grid of circuit connections configured for bonding to a substrate;

and

connecting said electrical terminals of said semiconductor die to said electrical connections of said substrate includes bonding said grid to connectors on said substrate.

73. The method of claim 72, wherein said heat sink member is attached to the non-active back side surface of said die.

74. The method of claim 69, wherein said substrate is a printed circuit board.

75. The method of claim 69, wherein covering said second side of said semiconductor die includes covering the second side of said semiconductor die with a thermally conductive gel elastomer filled with thermally conductive particles.

76. The method of claim 75, wherein said gel elastomer filled with thermally conductive particles comprises cross-linked silicone.

77. The method of claim 75, wherein said gel elastomer filled with thermally conductive particles includes a gel elastomer filled with metal particles.

78. The method of claim 77, wherein attaching said heat sink member includes attaching said heat sink member to the second side said semiconductor die with a non-stress thermally conductive adhesive.

79. The method of claim 78, wherein attaching said heat sink member includes attaching said heat sink member to the second side of said semiconductor die with a polymeric tape.

80. A method for fabricating a semiconductor device assembly having a heat sink, said method comprising:

providing a semiconductor die having a first side, a second side, and edges therebetween;

providing a substrate;

providing a thermally conductive heat sink member;

attaching the first side of said semiconductor die to said substrate;

covering at least a portion of the second side of said semiconductor die with a material having an exposed surface;

applying a material to encapsulate said edges of said semiconductor die edges;

maintaining said exposed surface of said material covering the second side of said semiconductor die substantially unencapsulated;

curing said material to encapsulate said edges of said semiconductor die;

removing said material having an exposed surface covering the second side of said semiconductor die; and

attaching said heat sink member to the second side of said semiconductor die.

81. The method of claim 80, wherein providing a semiconductor die includes providing a semiconductor die having wire bond pads;

and

wirebonding said wire bond pads of said semiconductor die to said substrate.

82. The method of claim 81, wherein said heat sink member is attached to said semiconductor die between said bond pads of said semiconductor die.

83. The method of claim 80, wherein providing a semiconductor die includes providing a semiconductor die having a surface having a grid of circuit connections configured for downbonding to a substrate;

and

attaching said semiconductor die to said substrate includes attaching said grid of circuit connections to said substrate.

84. The method of claim 83, wherein said heat sink member is attached to the non-active back side surface of said semiconductor die.

85. The method of claim 80, wherein said substrate is a printed circuit board.

86. The method of claim 80, wherein the covering the second side of said semiconductor die comprises includes covering the second side of said semiconductor die with a thermally conductive gel elastomer filled with thermally conductive particles.

87. The method of claim 86, wherein said thermally conductive gel elastomer comprises cross-linked silicone.

88. The method of claim 86, wherein said thermally conductive gel elastomer is filled with metal particles.

89. The method of claim 80, wherein attaching said heat sink includes attaching said heat sink member to the second side of said semiconductor die with a thermally conductive adhesive.

90. The method of claim 80, wherein attaching said heat sink includes attaching said heat sink member to the second side said semiconductor die with a polymeric tape.