Method of positioning semiconductor wafer

• US 6,433,352 B1
• Filed: 12/16/1999
• Issued: 08/13/2002
• Est. Priority Date: 12/17/1998
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Oka, Nobuhiko
• Primary Examiner(s): KRIZEK, JANICE LEE
• Application Number:
  US09/465,014
• Time in Patent Office: 971 Days
• Field of Search: 250/559.3, 356/400, 356/401
• US Class Current: 250/559.3
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors

Abstract

A method of positioning a semiconductor wafer includes the steps of fixing a semiconductor wafer on a wafer stage, the semiconductor wafer including a plurality of shot areas regularly arranged thereon, and positioning each of the shot areas in turn to an exposure position by a step and repeat system, wherein a step pitch to move each of the shot areas to the exposure position is adjusted by a magnitude of warpage of the semiconductor wafer.

Claims

1. A method of positioning a semiconductor wafer, the method comprising:

fixing a semiconductor wafer on a wafer stage, the semiconductor wafer including a plurality of shot areas regularly arranged thereon, and

positioning each of the shot areas in turn in an exposure position by a step and repeat system,

determining warpage of the semiconductor wafer using a plurality of linearly arranged alignment marks, wherein a first of the plurality of alignment marks is on a boundary of the shot area at the center of the semiconductor wafer and a last of the plurality of alignment marks is provided outside a shot area provided at the periphery of the semiconductor wafer and is the alignment mark of the plurality furthest from the center of the wafer, and total warpage magnitude is determined for the last alignment mark relative to a central area of the wafer; and

distributing the total warpage determined to the plurality of linearly arranged alignment marks in a manner so that warpage magnitude between pairs of adjacent alignment marks progressively increases moving away from the center of the wafer so that warpage magnitude distributed between second and third adjacent alignment marks of the plurality is less than warpage magnitude distributed between the third and a fourth alignment mark of the plurality, where the second, third and fourth alignment marks are located progressively further from the center of the wafer;

wherein a step pitch to move each of the shot areas to the exposure position is adjusted by a magnitude of warpage of the semiconductor wafer.

2. The method of claim 1 wherein at least one alignment mark is provided for each shot area on the semiconductor wafer.

3. The method of claim 2 wherein the magnitude of warpage of the semiconductor wafer is measured after the semiconductor wafer is positioned on the wafer stage.

4. The method of claim 2 wherein the step pitch is adjusted by a difference in magnitude of warpage between adjacent alignment marks.

5. The method of claim 1 wherein the magnitude of warpage of the semiconductor wafer is determined by measuring a difference in height between a central portion and a peripheral portion of the semiconductor wafer.

6. The method of claim 1 wherein the step pitch is adjusted based on a displacement of a center of the shot area, the displacement being calculated from the magnitude of warpage.

7. A method of positioning a semiconductor wafer, the method comprising:

fixing the semiconductor wafer on a horizontal wafer stage, the semiconductor wafer including a plurality of shot areas regularly arranged thereon,

positioning each of the shot areas in turn in an exposure position by a step and repeat system,

determining warpage of the semiconductor wafer using a plurality of linearly arranged alignment marks, wherein a first of the plurality of alignment marks is on a boundary of the shot area at the center of the semiconductor wafer and a last of the plurality of alignment marks is provided outside a shot area provided at the periphery of the semiconductor wafer and is the alignment mark of the plurality furthest from the center of the wafer, and total warpage magnitude is determined for the last alignment mark relative to a central area of the wafer,

distributing the total warpage magnitude to the plurality of alignment marks based on a curve bridged between the center of the wafer and the last of the plurality of alignment marks, the curve being predetermined by a size and material of the wafer, and

calculating horizontal distances between pairs of adjacent alignment marks from the distributed warpage magnitude, wherein a step pitch to move each of the shot areas to the exposure position is adjusted based on each calculated distance.