MOS-gated power device having segmented trench and extended doping zone and process for forming same

• US 6,433,385 B1
• Filed: 10/12/2000
• Issued: 08/13/2002
• Est. Priority Date: 05/19/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher B., Grebs, Thomas E., Ridley, Rodney S., Cumbo, Joseph L.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Wilson, Christian D.
• Application Number:
  US09/689,939
• Time in Patent Office: 670 Days
• Field of Search: 257/328, 257/329, 257/330, 438/259, 438/270
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the substrate in the upper layer comprises two segments having differing widths relative to one another: a bottom segment of lesser width filled with a dielectric material, and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, the filled upper segment of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from an upper surface into the upper layer of the substrate only on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench.

Claims

1. A trench MOS-gated device comprising:

a substrate including an upper layer, said substrate comprising doped monocrystalline semiconductor material of a first conduction type;

an extended trench in said upper layer, said trench comprising two segments having differing widths relative to one another, a bottom segment of lesser width filled with a dielectric material and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, said filled upper segment of said trench forming a gate region;

a doped extended zone of a second opposite conduction type extending from an upper surface into said upper layer on only one side of said extended trench;

a doped well region of said second conduction type overlying a drain zone of said first conduction type in said upper layer on the opposite side of said trench, said drain zone being substantially insulated from said extended zone by said bottom segment of said trench;

a heavily doped source region of said first conduction type and a heavily doped body region of said second conduction type disposed at said upper surface in said well region only on the side of said trench opposite said doped extended zone;

an interlevel dielectric layer on said upper surface overlying said gate and source regions; and

a metal layer overlying said upper surface and said interlevel dielectric layer, said metal layer being in electrical contact with said source and body regions and said extended zone.

2. The device of claim 1 further comprising:

a doped drain zone of said first conduction type extending through said upper layer and into said substrate beneath said well region and said extended zone.

3. The device of claim 2 further comprising:

a heavily doped drain zone of said first conduction type disposed at a lower surface of said substrate.

4. The device of claim 1 wherein said doped extended zone extends into said upper layer to a depth substantially equal to the depth of said extended trench.

5. The device of claim 1 wherein said widths of said trench upper segment and said trench bottom segment are in a ratio of about 1.2:

1 to about 12;

1.

6. The device of claim 5 wherein said widths are in a ratio of about 10:

1.

7. The device of claim 1 wherein said trench upper segment and said extended trench each extend to a selected depth, said depths of said upper segment and said extended trench being in a ratio, relative to one another, of about 1:

2 to about 1;

8.

8. The device of claim 7 wherein said depths are in a ratio of about 1:

5.

9. The device of claim 1 wherein said upper layer is an epitaxial layer.

10. The device of claim 1 wherein said substrate comprises monocrystalline silicon.

11. The device of claim 1 wherein said dielectric material comprises silicon dioxide.

12. The device of claim 1 wherein said conductive material in said upper segment of said trench comprises doped polysilicon.

13. The device of claim 1 wherein said first conduction type is N and said second conduction type is P.

14. The device of claim 1 wherein said device comprises a plurality of extended trenches.

15. The device of claim 14 wherein said plurality of extended trenches have an open-cell stripe topology.

16. The device of claim 14 wherein said plurality of extended trenches have a closed-cell cellular topology.

17. The device of claim 1 selected from the group consisting of a power MOSFET, an insulated gate bipolar transistor, and an MOS-controlled thyristor.