Methods and apparatus for optimizing semiconductor inspection tools

• US 6,433,561 B1
• Filed: 08/25/2000
• Issued: 08/13/2002
• Est. Priority Date: 12/14/1999
• Status: Expired due to Term

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Pinto, Gustavo A., Leslie, Brian C., Tsai, Bin-Ming Benjamin, Long, Robert Thomas, Satya, Akella V. S.
• Primary Examiner(s): Le, N.
• Assistant Examiner(s): Deb, Anjan K.
• Application Number:
  US09/648,096
• Time in Patent Office: 718 Days
• Field of Search: 324/753, 324/751, 324/752, 324/754, 324/750, 250/492.5, 356/237.4
• US Class Current: 356/237.5
• CPC Class Codes: G01N 21/66 electrically excited, e.g. electroluminescence
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01J 2237/2817 Pattern inspection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Disclosed is a method of inspecting a sample. At least a portion of the sample is illuminated. Signals received from the illuminated portion are detected, and the detected signals are processed to find defects present on the sample. The processing of the detected signals is optimized, at least in part, based upon results obtained from voltage contrast testing. In one implementation, the illumination is an optical illumination. In another embodiment, the processing comprises automated defect classification, and setup of the automated classification is optimized using the results obtained from voltage contrast testing. In another implementation, the results relate to a probability that a feature present on the sample represents an electrical defect.

Claims

1. A method of inspecting a sample, comprising:

in a first inspection system, illuminating at least a portion of the sample;

in a first inspection system, detecting signals received from the illuminated portion; and

in a first inspection system, processing the detected signals to find defects present on the sample, wherein the processing of the detected signals is optimized, at least in part, based upon results obtained from voltage contrast testing in a second inspection system.

2. The method of claim 1, wherein the illumination comprises optical illumination.

3. The method of claim 1, wherein at least a portion of the detected signals represent reflected light.

4. The method of claim 1, wherein at least a portion of the detected signals represent scattered light.

5. The method of claim 1, wherein the processing comprises automated defect classification.

6. The method of claim 5, wherein setup of the automated classification is optimized using the results obtained from voltage contrast testing.

7. The method of claim 6, wherein images of regions of the sample are reviewed during the setup, and wherein images associated with a higher likelihood of electrical defects are more readily identified as a result of the optimization.

8. The method of claim 5, wherein an algorithm used for the automated classification is optimized using the results obtained from voltage contrast testing.

9. The method of claim 1, wherein the results relate to a probability that a feature present on the sample represents an electrical defect.

10. The method of claim 9, wherein the defect is identified as adversely affecting yield of a semiconductor device present on the sample.

11. A method of optimizing an optical measurement tool, the method comprising:

a. inspecting a test structure via voltage contrast to determine a general location of one or more killer defects and to generate a first map of such killer defects;

b. optically inspecting the test structure to produce a plurality of optical images and a second map of optical defects; and

c. overlaying the first map and the second map to associate the optical defects with at least a portion of the killer defects and to determine whether an optical recipe is optimized for detection of killer defects.

12. A method as recited in claim 11 further comprising repeating steps (b) and (c) under different optical recipes until the optical recipe is optimized.

13. A method as recited in claim 11, wherein the optical inspection is performed on a first layer of the test structure that differs from a second layer of the test structure on which the voltage contrast inspection is performed.

14. A method as recited in claim 11 further comprising determining which manufacturing step is optimal for detecting killer defects.

15. A method as recited in claim 11 wherein the steps a through b are further used to periodically spot check or calibrate the optical recipes.

16. A method as recited in claim 11 further comprising associating the killer defects obtained during the voltage contrast inspection with one or more of the plurality of optical images to track a source of the killer defects.

17. A method as recited in claim 16, wherein it is determined which fabrication process is the source of the killer defects.

18. A method as recited in claim 11 further comprising:

obtaining a plurality of subsequent optical images; and

classifying one or more of the plurality of subsequently obtained optical defects as having killer defects when the one or more subsequent optical images are similar to the previously obtained optical images associated with the killer defects.