Apparatus for testing an integrated circuit in an oven during burn-in

• US 6,433,569 B1
• Filed: 10/12/2000
• Issued: 08/13/2002
• Est. Priority Date: 04/03/1996
• Status: Expired due to Fees

• Current Assignee: Orchard Holdings, LLC
• Original Assignee: Pycon, Inc.
• Inventors: Prakash, Kombupalayam M., Eliashberg, Victor M.
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US09/689,997
• Time in Patent Office: 670 Days
• Field of Search: 324/760, 324/763, 324/765, 324/158.1, 365/201, 714/718, 714/719, 714/720
• US Class Current: 324/750.05
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads

Abstract

An apparatus for testing an integrated circuit in an oven during burn-in. A burn-in board in the oven is electrically connected to a plurality of integrated circuit (“ICE”) components. A driver/interface board outside the oven is electrically connected to the burn-in board through a plurality of contacts and sends and receives a plurality of signals between the IC components and a test controller. A switch module on the burn-in board comprises a plurality of high-temperature switches for transferring signals between the plurality of IC components and the driver/interface board during burn-in. A plurality of signals entering the switch module from the driver/interface board does not exceed in number the plurality of contacts, and is fewer in number than a plurality of signals exiting the switch module to the plurality of IC components.

Claims

1. A method for testing an integrated circuit (“

IC”

) memory during burn-in, the method comprising;

placing the IC memory in a heated oven;

selecting the IC memory;

writing a data word to the IC memory, a first half of the data word being transferred on a first set of data lines, a second half of the data word being transferred on a second set of data lines, the first set of data lines and the second set of data lines each receiving signals from a set of shared data lines;

reading the IC memory, comprising;

reading a first half of a data word from the IC memory; and

reading a second half of the data word from the IC memory;

wherein the first half and the second half of the data word in the IC memory are each transferred on the set of shared data lines.

2. The method of claim 1, further comprising comparing data written to the IC memory with data read from the IC memory.

3. The method of claim 2, further comprising designating the IC memory as having failed if the data read from the IC memory does not match the data written to the IC memory.