Heterogeneous programmable gate array

• US 6,433,578 B1
• Filed: 05/05/2000
• Issued: 08/13/2002
• Est. Priority Date: 05/07/1999
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: MorphICs Technology, Inc. (Infineon Technologies AG)
• Inventors: Wasson, Stephen L.
• Primary Examiner(s): LE, DON P
• Application Number:
  US09/565,648
• Time in Patent Office: 830 Days
• Field of Search: 326/37-41
• US Class Current: 326/38
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A heterogeneous programmable gate array has an unstructured logic sub-array and a structured logic sub-array. An unstructured input/output interconnect structure delivers unstructured-to-unstructured input/output signals to the unstructured logic sub-array, while a bussed input/output interconnect structure delivers structured-to-structured input/output signals to the structured logic sub-array. A control signal bus is connected between the unstructured logic sub-array and the structured logic sub-array to deliver unstructured source signals therebetween. A bussed signal bus is connected between the unstructured logic sub-array and the structured logic sub-array to deliver structured source signals therebetween.

Claims

1. A heterogeneous programmable gate array comprising:

an unstructured logic sub-array of identical unstructured logic elements in a first contiguous area of said programmable gate array;

an unstructured input/output interconnect structure to deliver unstructured-to-unstructured input/output signals only to elements of said unstructured logic sub-array;

a structured logic sub-array of identical structured logic elements in a second contiguous area of said programmable gate array, said elements of said structured logic sub-array being complementary to said elements of said unstructured logic sub-array;

a bussed input/output interconnect structure to deliver structured-to-structured input/output signals only to elements of said structured logic sub-array;

a control signal bus coupled between said unstructured logic sub-array and said structured logic sub-array to deliver unstructured source signals therebetween; and

a bussed signal bus connected between said unstructured logic sub-array and said structured logic sub-array to deliver structured source signals therebetween.

2. The heterogeneous programmable gate array of claim 1, wherein said unstructured logic sub-array implements a state machine.

3. The heterogeneous programmable gate array of claim 1, wherein said unstructured logic sub-array implements a decoder.

4. The heterogeneous programmable gate array of claim 1, wherein said unstructured logic sub-array is characterized by routing resources that are dense, short, low fan-out, and high skew.

5. The heterogeneous programmable gate array of claim 1, wherein said structured logic sub-array implements an arithmetic function.

6. The heterogeneous programmable gate array of claim 1, wherein said structured logic sub-array implements a storage register.

7. The heterogeneous programmable gate array of claim 1, wherein said structured logic sub-array implements random access memory.

8. The heterogeneous programmable gate array of claim 1, wherein said structured logic sub-array is characterized by routing resources that are sparse, long, high fan-out, and low skew.

9. The heterogeneous programmable gate array of claim 1, wherein said gate array includes approximately one-tenth to four-tenths unstructured logic sub-array circuitry and approximately nine-tenths to six-tenths structured logic sub-array circuitry.