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SOI CMOS dynamic circuits having threshold voltage control

  • US 6,433,587 B1
  • Filed: 03/17/2000
  • Issued: 08/13/2002
  • Est. Priority Date: 03/17/2000
  • Status: Expired due to Fees
First Claim
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1. A logic circuit formed in an SOI type substrate and having a first input for receiving an evaluate signal and a plurality of logic inputs for receiving signals to be logically evaluated, comprising:

  • circuitry formed in the SOI type substrate and coupled to a body of at least one internal FET of the logic circuit and also coupled to a voltage terminal;

    said circuit having a second input for receiving a clock signal having at least two alternating voltage levels, the second input coupled to the circuitry for effectuating a temporary pull down of the voltage level of the body in response to one of the clocks signal'"'"'s voltage levels; and

    wherein the voltage level of the body is pulled to the voltage terminal level just prior to an evaluate phase of logic circuit.

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